Imre Deak <imre.deak@xxxxxxxxx> writes: > [ text/plain ] > When determining whether CDCLK is enabled by BIOS and so we should skip > reprogramming it, we didn't check the related DBUF power request and > state. In theory BIOS could enable one without the other so check for > this case and reprogram things if something is amiss. > > Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_display.c | 28 ++++++++++++++++++++++++++-- > 1 file changed, 26 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 1fbe619..447d46e 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5440,14 +5440,38 @@ static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency) > intel_update_cdclk(dev_priv->dev); > } > > +static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv) > +{ > + if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE)) > + return false; > + > + /* TODO: Check for a valid CDCLK rate */ > + Discussed about the pll lock in irc with Imre. I think pll lock bit should be included in the sanity inspection here too. But that can be follow ups. Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> > + if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) { > + DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n"); > + > + return false; > + } > + > + if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) { > + DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n"); > + > + return false; > + } > + > + return true; > +} > + > void broxton_init_cdclk(struct drm_i915_private *dev_priv) > { > /* check if cd clock is enabled */ > - if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { > - DRM_DEBUG_KMS("Display already initialized\n"); > + if (broxton_cdclk_is_enabled(dev_priv)) { > + DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n"); > return; > } > > + DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n"); > + > /* > * FIXME: > * - The initial CDCLK needs to be read from VBT. > -- > 2.5.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx