On Wed, 2016-04-06 at 17:23 +0530, Durgadoss R wrote: > Currently, the required shared dpll is saved in the crtc_state. > Similarly, this patch saves the dpll config values also, so that > these values (through crtc_state->shared_dpll->config.hw_state) > can be used for upfront link training. > > Signed-off-by: Durgadoss R <durgadoss.r@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c > b/drivers/gpu/drm/i915/intel_dpll_mgr.c > index 1175eeb..cad10f2 100644 > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c > @@ -248,6 +248,7 @@ intel_reference_shared_dpll(struct intel_shared_dpll *pll, > pipe_name(crtc->pipe)); > > intel_shared_dpll_config_get(shared_dpll, pll, crtc); > + crtc_state->shared_dpll->config = shared_dpll[i]; This overwrites the state stored in dev_priv->shared_dpll[i].config, so it means we loose the current state set in the hardware. If the atomic check fails after this, the software tracking of the hw state gets messed up. Ander > } > > void intel_shared_dpll_commit(struct drm_atomic_state *state) --------------------------------------------------------------------- Intel Finland Oy Registered Address: PL 281, 00181 Helsinki Business Identity Code: 0357606 - 4 Domiciled in Helsinki This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
