Along with below patches sharing some background details/design. - On BXT, Display cannot generate an interrupt when in D3. - Without display in D3, S0ix can be achieved, Power impact will be zero if d3 is blocked. PMCSR for Graphics/Display is irrelevant, as the power management for them is taken care by the PUNIT using RC6/DC9 hints and *not* through PMCSR write trigger. So solution is based on below principles: - Display should not be put into D3 for HPD to work. - With D0+DC9 we can achieve S0ix and at the same time helps to get the interrupt. - Using pci_save_state() during suspend to take control from OSPM and blocking D3, while resuming, giving back to OSPM by pci_restore_state(). - _DSM method is used to program pmc hpd control register to enable hpd during suspend. Please have a look and send your comments/suggestions. Animesh Manna (6): drm/i915/bxt: VBT changes for hpd as wakeup feature drm/i915/bxt: Added _DSM call to set HPD_CTL. drm/i915/bxt: Corrected the guid for bxt. drm/i915/bxt: Block D3 during suspend. drm/i915: Enable HPD interrupts with master ctl interrupt drm/i915/bxt: Enable HPD during suspend. drivers/gpu/drm/i915/i915_drv.c | 6 ++++ drivers/gpu/drm/i915/i915_drv.h | 8 +++++ drivers/gpu/drm/i915/i915_irq.c | 56 +++++++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 13 ++++++++ drivers/gpu/drm/i915/intel_acpi.c | 53 ++++++++++++++++++++++++++++----- drivers/gpu/drm/i915/intel_bios.c | 7 +++++ drivers/gpu/drm/i915/intel_vbt_defs.h | 3 +- 7 files changed, 134 insertions(+), 12 deletions(-) -- 2.0.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
