On Thu, 07 Apr 2016, Ramalingam C <ramalingam.c@xxxxxxxxx> wrote: > At BXT DSI, PIPE registers are inactive. So we can't get the > PIPE's mode parameters from them. The possible option is > retriving them from the PORT registers. > > The required changes are added for BXT in intel_dsi_get_config > (encoder->get_config). > > v2: Addressed the Jani's comments > -removed the redundant call to encoder->get_config > -read bpp from port register > -removed retrival of src_size from encoder->get_config > > v3: pipe_config->pipe_bpp is fixed > Jani's review comments addressed: > Few horizontal timing parameters dropped from the patch to make > progress, as there seems to be some disagreement on > best/feasible/possible options. > > Signed-off-by: Ramalingam C <ramalingam.c@xxxxxxxxx> > Signed-off-by: Uma Shankar <uma.shankar@xxxxxxxxx> > > Previously Reviewed at: https://lists.freedesktop.org/archives/intel-gfx/2016-April/091737.html Both pushed to drm-intel-next-queued, thanks for the patches. BR, Jani. > --- > drivers/gpu/drm/i915/intel_dsi.c | 60 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 60 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c > index a0f374f..a1e0547 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -758,14 +758,74 @@ out_put_power: > return active; > } > > +static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, > + struct intel_crtc_state *pipe_config) > +{ > + struct drm_device *dev = encoder->base.dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct drm_display_mode *adjusted_mode = > + &pipe_config->base.adjusted_mode; > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > + unsigned int bpp, fmt; > + enum port port; > + u16 vfp, vsync, vbp; > + > + /* > + * Atleast one port is active as encoder->get_config called only if > + * encoder->get_hw_state() returns true. > + */ > + for_each_dsi_port(port, intel_dsi->ports) { > + if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) > + break; > + } > + > + fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; > + pipe_config->pipe_bpp = > + mipi_dsi_pixel_format_to_bpp( > + pixel_format_from_register_bits(fmt)); > + bpp = pipe_config->pipe_bpp; > + > + /* In terms of pixels */ > + adjusted_mode->crtc_hdisplay = > + I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); > + adjusted_mode->crtc_vdisplay = > + I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); > + adjusted_mode->crtc_vtotal = > + I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); > + > + /* > + * TODO: Retrieve hfp, hsync and hbp. Adjust them for dual link and > + * calculate hsync_start, hsync_end, htotal and hblank_end > + */ > + > + /* vertical values are in terms of lines */ > + vfp = I915_READ(MIPI_VFP_COUNT(port)); > + vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port)); > + vbp = I915_READ(MIPI_VBP_COUNT(port)); > + > + adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; > + > + adjusted_mode->crtc_vsync_start = > + vfp + adjusted_mode->crtc_vdisplay; > + adjusted_mode->crtc_vsync_end = > + vsync + adjusted_mode->crtc_vsync_start; > + adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; > + adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; > +} > + > + > static void intel_dsi_get_config(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config) > { > + struct drm_device *dev = encoder->base.dev; > u32 pclk; > DRM_DEBUG_KMS("\n"); > > pipe_config->has_dsi_encoder = true; > > + if (IS_BROXTON(dev)) > + bxt_dsi_get_pipe_config(encoder, pipe_config); > + > /* > * DPLL_MD is not used in case of DSI, reading will get some default value > * set dpll_md = 0 -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
