On Fri, Apr 01, 2016 at 04:02:36PM +0300, Imre Deak wrote:
> So far we only power well enabling was synchronous not disabling. Since
> we don't exactly know how the firmware (both DMC and PCU) synchronizes
> against the actual power well state during DC transitions, make the
> disabling also synchronous.
>
> CC: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
> CC: Patrik Jakobsson <patrik.jakobsson@xxxxxxxxxxxxxxx>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index d20fd8f..f5f6e89 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -720,10 +720,6 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
>
> if (!is_enabled) {
> DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
> - if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
> - state_mask), 1))
> - DRM_ERROR("%s enable timeout\n",
> - power_well->name);
> check_fuse_status = true;
> }
> } else {
> @@ -737,6 +733,11 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> bxt_sanitize_power_well_requests(dev_priv, power_well);
> }
>
> + if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
> + 1))
> + DRM_ERROR("%s %s timeout\n",
> + power_well->name, enable ? "enable" : "disable");
> +
> if (check_fuse_status) {
> if (power_well->data == SKL_DISP_PW_1) {
> if (wait_for((I915_READ(SKL_FUSE_STATUS) &
> --
> 2.5.0
>
--
---
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