return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0715bb7..cbf8a03 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2169,6 +2169,17 @@ int i915_ppgtt_init_hw(struct drm_device *dev) {
gtt_write_workarounds(dev);
+ if (HAS_TRTT(dev) && USES_FULL_48BIT_PPGTT(dev)) {
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ /*
+ * Globally enable TR-TT support in Hw.
+ * Still TR-TT enabling on per context basis is required.
+ * Non-trtt contexts are not affected by this setting.
+ */
+ I915_WRITE(GEN9_TR_CHICKEN_BIT_VECTOR,
+ GEN9_TRTT_BYPASS_DISABLE);
+ }
+
/* In the case of execlists, PPGTT is enabled by the context
descriptor
* and the PDPs are contained within the context itself. We don't
* need to do anything here. */
@@ -3362,6 +3373,60 @@
i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj,
}
+void intel_trtt_context_destroy_vma(struct i915_vma *vma) {
+ struct i915_address_space *vm = vma->vm;
+
+ WARN_ON(!list_empty(&vma->obj_link));
+ WARN_ON(!list_empty(&vma->vm_link));
+ WARN_ON(!list_empty(&vma->exec_list));
+
+ WARN_ON(!vma->pin_count);
+
+ if (drm_mm_node_allocated(&vma->node))
+ drm_mm_remove_node(&vma->node);
+
+ i915_ppgtt_put(i915_vm_to_ppgtt(vm));
+ kmem_cache_free(to_i915(vm->dev)->vmas, vma); }
+
+struct i915_vma *
+intel_trtt_context_allocate_vma(struct i915_address_space *vm,
+ uint64_t segment_base_addr)
+{
+ struct i915_vma *vma;
+ int ret;
+
+ vma = kmem_cache_zalloc(to_i915(vm->dev)->vmas, GFP_KERNEL);
+ if (!vma)
+ return ERR_PTR(-ENOMEM);
+
+ INIT_LIST_HEAD(&vma->obj_link);
+ INIT_LIST_HEAD(&vma->vm_link);
+ INIT_LIST_HEAD(&vma->exec_list);
+ vma->vm = vm;
+ i915_ppgtt_get(i915_vm_to_ppgtt(vm));
+
+ /* Mark the vma as permanently pinned */
+ vma->pin_count = 1;
+
+ /* Reserve from the 48 bit PPGTT space */
+ vma->node.start = segment_base_addr;
+ vma->node.size = GEN9_TRTT_SEGMENT_SIZE;
+ ret = drm_mm_reserve_node(&vm->mm, &vma->node);
+ if (ret) {
+ ret = i915_gem_evict_for_vma(vma);
+ if (ret == 0)
+ ret = drm_mm_reserve_node(&vm->mm, &vma-
node);
+ }
+ if (ret) {
+ intel_trtt_context_destroy_vma(vma);
+ return ERR_PTR(ret);
+ }
+
+ return vma;
+}
+
static struct scatterlist *
rotate_pages(const dma_addr_t *in, unsigned int offset,
unsigned int width, unsigned int height, diff --git
a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index d804be0..8cbaca2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -128,6 +128,10 @@ typedef uint64_t gen8_ppgtt_pml4e_t;
#define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
#define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
+/* Fixed size segment */
+#define GEN9_TRTT_SEG_SIZE_SHIFT 44
+#define GEN9_TRTT_SEGMENT_SIZE (1ULL <<
GEN9_TRTT_SEG_SIZE_SHIFT)
+
enum i915_ggtt_view_type {
I915_GGTT_VIEW_NORMAL = 0,
I915_GGTT_VIEW_ROTATED,
@@ -560,4 +564,8 @@ size_t
i915_ggtt_view_size(struct drm_i915_gem_object *obj,
const struct i915_ggtt_view *view);
+struct i915_vma *
+intel_trtt_context_allocate_vma(struct i915_address_space *vm,
+ uint64_t segment_base_addr);
+void intel_trtt_context_destroy_vma(struct i915_vma *vma);
#endif
diff --git a/drivers/gpu/drm/i915/i915_reg.h
b/drivers/gpu/drm/i915/i915_reg.h index 264885f..07936b6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -188,6 +188,25 @@ static inline bool i915_mmio_reg_valid(i915_reg_t
reg)
#define GEN8_RPCS_EU_MIN_SHIFT 0
#define GEN8_RPCS_EU_MIN_MASK (0xf <<
GEN8_RPCS_EU_MIN_SHIFT)
+#define GEN9_TR_CHICKEN_BIT_VECTOR _MMIO(0x4DFC)
+#define GEN9_TRTT_BYPASS_DISABLE (1 << 0)
+
+/* TRTT registers in the H/W Context */
+#define GEN9_TRTT_L3_POINTER_DW0 _MMIO(0x4DE0)
+#define GEN9_TRTT_L3_POINTER_DW1 _MMIO(0x4DE4)
+#define GEN9_TRTT_L3_GFXADDR_MASK 0xFFFFFFFF0000
+
+#define GEN9_TRTT_NULL_TILE_REG _MMIO(0x4DE8)
+#define GEN9_TRTT_INVD_TILE_REG _MMIO(0x4DEC)
+
+#define GEN9_TRTT_VA_MASKDATA _MMIO(0x4DF0)
+#define GEN9_TRVA_MASK_VALUE 0xF0
+#define GEN9_TRVA_DATA_MASK 0xF
+
+#define GEN9_TRTT_TABLE_CONTROL _MMIO(0x4DF4)
+#define GEN9_TRTT_IN_GFX_VA_SPACE (1 << 1)
+#define GEN9_TRTT_ENABLE (1 << 0)
+
#define GAM_ECOCHK _MMIO(0x4090)
#define BDW_DISABLE_HDC_INVALIDATION (1<<25)
#define ECOCHK_SNB_BIT (1<<10)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c
b/drivers/gpu/drm/i915/intel_lrc.c
index 3a23b95..8af480b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1645,6 +1645,76 @@ static int gen9_init_render_ring(struct
intel_engine_cs *engine)
return init_workarounds_ring(engine);
}
+static int gen9_init_rcs_context_trtt(struct drm_i915_gem_request *req)
+{
+ struct intel_ringbuffer *ringbuf = req->ringbuf;
+ int ret;
+
+ ret = intel_logical_ring_begin(req, 2 + 2);
+ if (ret)
+ return ret;
+
+ intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
+
+ intel_logical_ring_emit_reg(ringbuf, GEN9_TRTT_TABLE_CONTROL);
+ intel_logical_ring_emit(ringbuf, 0);
+
+ intel_logical_ring_emit(ringbuf, MI_NOOP);
+ intel_logical_ring_advance(ringbuf);
+
+ return 0;
+}
+
+static int gen9_emit_trtt_regs(struct drm_i915_gem_request *req) {
+ struct intel_context *ctx = req->ctx;
+ struct intel_ringbuffer *ringbuf = req->ringbuf;
+ u64 masked_l3_gfx_address =
+ ctx->trtt_info.l3_table_address &
GEN9_TRTT_L3_GFXADDR_MASK;
+ u32 trva_data_value =
+ (ctx->trtt_info.segment_base_addr >>
GEN9_TRTT_SEG_SIZE_SHIFT) &
+ GEN9_TRVA_DATA_MASK;
+ const int num_lri_cmds = 6;
+ int ret;
+
+ /*
+ * Emitting LRIs to update the TRTT registers is most reliable, instead
+ * of directly updating the context image, as this will ensure that
+ * update happens in a serialized manner for the context and also
+ * lite-restore scenario will get handled.
+ */
+ ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2);
+ if (ret)
+ return ret;
+
+ intel_logical_ring_emit(ringbuf,
MI_LOAD_REGISTER_IMM(num_lri_cmds));
+
+ intel_logical_ring_emit_reg(ringbuf,
GEN9_TRTT_L3_POINTER_DW0);
+ intel_logical_ring_emit(ringbuf,
+lower_32_bits(masked_l3_gfx_address));
+
+ intel_logical_ring_emit_reg(ringbuf,
GEN9_TRTT_L3_POINTER_DW1);
+ intel_logical_ring_emit(ringbuf,
+upper_32_bits(masked_l3_gfx_address));
+
+ intel_logical_ring_emit_reg(ringbuf, GEN9_TRTT_NULL_TILE_REG);
+ intel_logical_ring_emit(ringbuf, ctx->trtt_info.null_tile_val);
+
+ intel_logical_ring_emit_reg(ringbuf, GEN9_TRTT_INVD_TILE_REG);
+ intel_logical_ring_emit(ringbuf, ctx->trtt_info.invd_tile_val);
+
+ intel_logical_ring_emit_reg(ringbuf, GEN9_TRTT_VA_MASKDATA);
+ intel_logical_ring_emit(ringbuf,
+ GEN9_TRVA_MASK_VALUE |
trva_data_value);
+
+ intel_logical_ring_emit_reg(ringbuf, GEN9_TRTT_TABLE_CONTROL);
+ intel_logical_ring_emit(ringbuf,
+ GEN9_TRTT_IN_GFX_VA_SPACE |
GEN9_TRTT_ENABLE);
+
+ intel_logical_ring_emit(ringbuf, MI_NOOP);
+ intel_logical_ring_advance(ringbuf);
+
+ return 0;
+}
+
static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
{
struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; @@ -2003,6
+2073,25 @@ static int gen8_init_rcs_context(struct drm_i915_gem_request
*req)
return intel_lr_context_render_state_init(req);
}
+static int gen9_init_rcs_context(struct drm_i915_gem_request *req) {
+ int ret;
+
+ /*
+ * Explictily disable TR-TT at the start of a new context.
+ * Otherwise on switching from a TR-TT context to a new Non TR-TT
+ * context the TR-TT settings of the outgoing context could get
+ * spilled on to the new incoming context as only the Ring Context
+ * part is loaded on the first submission of a new context, due to
+ * the setting of ENGINE_CTX_RESTORE_INHIBIT bit.
+ */
+ ret = gen9_init_rcs_context_trtt(req);
+ if (ret)
+ return ret;
+
+ return gen8_init_rcs_context(req);
+}
+
/**
* intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
*
@@ -2134,11 +2223,14 @@ static int logical_render_ring_init(struct
drm_device *dev)
logical_ring_default_vfuncs(dev, engine);
/* Override some for render ring. */
- if (INTEL_INFO(dev)->gen >= 9)
+ if (INTEL_INFO(dev)->gen >= 9) {
engine->init_hw = gen9_init_render_ring;
- else
+ engine->init_context = gen9_init_rcs_context;
+ } else {
engine->init_hw = gen8_init_render_ring;
- engine->init_context = gen8_init_rcs_context;
+ engine->init_context = gen8_init_rcs_context;
+ }
+
engine->cleanup = intel_fini_pipe_control;
engine->emit_flush = gen8_emit_flush_render;
engine->emit_request = gen8_emit_request_render; @@ -2702,3
+2794,29 @@ void intel_lr_context_reset(struct drm_device *dev,
ringbuf->tail = 0;
}
}
+
+int intel_lr_rcs_context_setup_trtt(struct intel_context *ctx) {
+ struct intel_engine_cs *engine = &(ctx->i915->engine[RCS]);
+ struct drm_i915_gem_request *req;
+ int ret;
+
+ if (!ctx->engine[RCS].state) {
+ ret = intel_lr_context_deferred_alloc(ctx, engine);
+ if (ret)
+ return ret;
+ }
+
+ req = i915_gem_request_alloc(engine, ctx);
+ if (IS_ERR(req))
+ return PTR_ERR(req);
+
+ ret = gen9_emit_trtt_regs(req);
+ if (ret) {
+ i915_gem_request_cancel(req);
+ return ret;
+ }
+
+ i915_add_request(req);
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/intel_lrc.h
b/drivers/gpu/drm/i915/intel_lrc.h
index a17cb12..f3600b2 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -107,6 +107,7 @@ void intel_lr_context_reset(struct drm_device *dev,
struct intel_context *ctx);
uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
struct intel_engine_cs *engine);
+int intel_lr_rcs_context_setup_trtt(struct intel_context *ctx);
u32 intel_execlists_ctx_id(struct intel_context *ctx,
struct intel_engine_cs *engine);
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index a5524cc..604da23 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1167,7 +1167,15 @@ struct drm_i915_gem_context_param {
#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
+#define I915_CONTEXT_PARAM_TRTT 0x4
__u64 value;
};
+struct drm_i915_gem_context_trtt_param {
+ __u64 segment_base_addr;
+ __u64 l3_table_address;
+ __u32 invd_tile_val;
+ __u32 null_tile_val;
+};
+
#endif /* _UAPI_I915_DRM_H_ */
--
1.9.2
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