On Thu, Mar 24, 2016 at 03:42:28PM +0100, Maarten Lankhorst wrote: > Op 24-03-16 om 15:26 schreef Ville Syrjälä: > > On Thu, Mar 24, 2016 at 09:35:04AM +0100, Maarten Lankhorst wrote: > >> Op 23-03-16 om 16:07 schreef Ville Syrjälä: > >>> On Wed, Mar 23, 2016 at 02:24:30PM +0100, Maarten Lankhorst wrote: > >>>> Rename intel_unpin_work to intel_flip_work and use it for mmio flips > >>>> and unpinning. Use flip_queued_req to hold the wait request in the > >>>> mmio case and allow the vblank interrupt to complete mmio work to > >>>> have mmio flips run correctly on g4 and earlier. > >>> Before you actually go and trust drm_vblank_count() you should make it > >>> race free. > >> How about adding the below to the patch? > > You can't just mix the hw and sw counter. Using the hw counter would be > > neat because it doesn't require so much work to be race-free, but that > > leaves out gen2 which I don't like. My atomic code used the hw counter > > though, but I had plans to fall back to the sw counter on gen2 > > eventually. > > > So I dug in a little bit more.. > > MMIO updates don't require accurate vblank count for anything, so even if it was completely removed it would work. Yes they do if you want to use the vblank irq for completing them. > The only thing it's used for is for cs flips, if more than 1 vblank passed since submission, the request gets a rps boost. > > If more than 3 vblanks have passed after the request the cs flip waits on completed, the cs page flip is considered stuck > and will be forcefully completed. > > With stale values the worst case rps boost might get applied right away, or the cs flip is forcefully completed after only 2 vblanks. > Neither affects mmio flips, so ignore this extra hunk and look at the original patch. :) > > ~Maarten -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
