Re: [PATCH 5/5] drm/i915: Bump command parser version for new whitelisted registers

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On Tue, Mar 08, 2016 at 02:07:03PM -0800, Francisco Jerez wrote:
> Jordan Justen <jordan.l.justen@xxxxxxxxx> writes:
> 
> > Signed-off-by: Jordan Justen <jordan.l.justen@xxxxxxxxx>
> 
> Reviewed-by: Francisco Jerez <currojerez@xxxxxxxxxx>

Entire series applied to dinq, thanks for patches&review.
-Daniel

> 
> > ---
> >  drivers/gpu/drm/i915/i915_cmd_parser.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > index e1608da..f8381be 100644
> > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > @@ -1287,6 +1287,7 @@ int i915_cmd_parser_get_version(void)
> >  	 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
> >  	 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
> >  	 * 5. GPGPU dispatch compute indirect registers.
> > +	 * 6. TIMESTAMP register and Haswell CS GPR registers
> >  	 */
> > -	return 5;
> > +	return 6;
> >  }
> > -- 
> > 2.7.0
> >
> > _______________________________________________
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> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx




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-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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