On Wed, 16 Mar 2016, Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> On Tue, Mar 15, 2016 at 09:51:12PM +0200, Jani Nikula wrote:
>> BXT isn't as limited as BYT and CHT regarding DSI pipes and ports.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> drivers/gpu/drm/i915/intel_dsi.c | 14 +++++++++++++-
>> 2 files changed, 14 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 7dfc4007f3fa..a5035991dd57 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -8144,6 +8144,7 @@ enum skl_disp_power_wells {
>> #define READ_REQUEST_PRIORITY_HIGH (3 << 3)
>> #define RGB_FLIP_TO_BGR (1 << 2)
>>
>> +#define BXT_PIPE_SELECT_SHIFT 7
>> #define BXT_PIPE_SELECT_MASK (7 << 7)
>> #define BXT_PIPE_SELECT(pipe) ((pipe) << 7)
>
> These defines look a little misplaced, but that's separate topic.
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Pushed patches 1-4 to drm-intel-next-queued, as they are mostly
harmless. Fixed the eDP string to match spec in the earlier patch.
BR,
Jani.
>
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> index 6574b9ac3698..73c15210fdb1 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -700,7 +700,19 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>> if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
>> continue;
>>
>> - *pipe = port == PORT_A ? PIPE_A : PIPE_B;
>> + if (IS_BROXTON(dev_priv)) {
>> + u32 tmp = I915_READ(MIPI_CTRL(port));
>> + tmp &= BXT_PIPE_SELECT_MASK;
>> + tmp >>= BXT_PIPE_SELECT_SHIFT;
>> +
>> + if (WARN_ON(tmp > PIPE_C))
>> + continue;
>> +
>> + *pipe = tmp;
>> + } else {
>> + *pipe = port == PORT_A ? PIPE_A : PIPE_B;
>> + }
>> +
>> active = true;
>> break;
>> }
>> --
>> 2.1.4
--
Jani Nikula, Intel Open Source Technology Center
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