Re: [PATCH v2 (rebased) 3/4] drm/i915: Move pll power state to crtc power domains.

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On Mon, 2016-03-14 at 09:27 +0100, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>

Reviewed-by: Ander Conselvan de Oliveira <conselvan2@xxxxxxxxx>

> ---
>  drivers/gpu/drm/i915/intel_display.c  | 6 +++---
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 ----
>  2 files changed, 3 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 17d07a729cc0..dd76df70c62a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5276,6 +5276,9 @@ static unsigned long get_crtc_power_domains(struct
> drm_crtc *crtc,
>  		mask |= BIT(intel_display_port_power_domain(intel_encoder));
>  	}
>  
> +	if (crtc_state->shared_dpll)
> +		mask |= BIT(POWER_DOMAIN_PLLS);
> +
>  	return mask;
>  }
>  
> @@ -15729,9 +15732,6 @@ static void intel_modeset_readout_hw_state(struct
> drm_device *dev)
>  
>  		DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on
> %i\n",
>  			      pll->name, pll->config.crtc_mask, pll->on);
> -
> -		if (pll->config.crtc_mask)
> -			intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
>  	}
>  
>  	for_each_intel_encoder(dev, encoder) {
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 213862e8cd04..a9084c7c3a36 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -135,8 +135,6 @@ void intel_enable_shared_dpll(struct intel_crtc *crtc)
>  	}
>  	WARN_ON(pll->on);
>  
> -	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
> -
>  	DRM_DEBUG_KMS("enabling %s\n", pll->name);
>  	pll->funcs.enable(dev_priv, pll);
>  	pll->on = true;
> @@ -173,8 +171,6 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc)
>  	DRM_DEBUG_KMS("disabling %s\n", pll->name);
>  	pll->funcs.disable(dev_priv, pll);
>  	pll->on = false;
> -
> -	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
>  }
>  
>  static struct intel_shared_dpll *
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