On Wed, Mar 16, 2016 at 10:56:33AM +0200, Jani Nikula wrote: > On Tue, 15 Mar 2016, ville.syrjala@xxxxxxxxxxxxxxx wrote: > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > Compute the DSI PLL parameters during .compute_config() rather than > > .pre_pll_enable() so that we can fail gracefully if we can't find > > suitable parameters. > > > > In order to do that we need to store the DSI PLL parameters in > > pipe_config. > > > > v2: Handle BXT too > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > [snip] > > > @@ -317,15 +328,9 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) > > return 0; > > } > > > > - dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) & > > - BXT_DSI_PLL_RATIO_MASK; > > + config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL); > > > > - /* Invalid DSI ratio ? */ > > - if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || > > - dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { > > - DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio); > > - return 0; > > - } > > So you expect this to show up in the state checker instead now? Frankly I'm not expecting it to show up at all. If the BIOS does program an invalid value, well, then we should sanitize it somewhere without spewing errors. If we misprogram it, then the state checker could catch it (unless we have a bug in the compute phase already and somehow compute the correct clock w/ an incorrect ratio). > > Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx> > > > > -- > Jani Nikula, Intel Open Source Technology Center -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx