On Tue, 15 Mar 2016, ville.syrjala@xxxxxxxxxxxxxxx wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Supposedly the power sequencer still locks out the DPLL registers on > CHV, so let's issue a warning if it's still locked when enabling the > DPLL. > > Also drop the redundant IS_MOBILE() check for VLV when we check the same > thing. > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_display.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 638ce97777de..d3332a33f8a7 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1579,8 +1579,7 @@ static void vlv_enable_pll(struct intel_crtc *crtc, > assert_pipe_disabled(dev_priv, pipe); > > /* PLL is protected by panel, make sure we can write it */ > - if (IS_MOBILE(dev_priv->dev)) > - assert_panel_unlocked(dev_priv, pipe); > + assert_panel_unlocked(dev_priv, pipe); > > I915_WRITE(reg, dpll); > POSTING_READ(reg); > @@ -1615,6 +1614,9 @@ static void chv_enable_pll(struct intel_crtc *crtc, > > assert_pipe_disabled(dev_priv, pipe); > > + /* PLL is protected by panel, make sure we can write it */ > + assert_panel_unlocked(dev_priv, pipe); > + > mutex_lock(&dev_priv->sb_lock); > > /* Enable back the 10bit clock to display controller */ -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
