The only steps requiring device access is the fence and swizzling
initialization, so split these out keeping them in their current place
and move the rest of init steps earlier.
Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_dma.c | 13 ++++++++-----
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem.c | 34 ++++++++++++++++++++--------------
3 files changed, 29 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index da96ccd..9ada500 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1031,6 +1031,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
intel_init_display_hooks(dev_priv);
intel_init_clock_gating_hooks(dev_priv);
intel_init_audio_hooks(dev_priv);
+ i915_gem_load_init(dev);
intel_runtime_pm_get(dev_priv);
@@ -1114,7 +1115,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
intel_opregion_setup(dev);
- i915_gem_load_init(dev);
+ i915_gem_load_init_fences(dev_priv);
+ i915_gem_detect_bit_6_swizzle(dev);
+
i915_gem_shrinker_init(dev_priv);
/* On the 945G/GM, the chipset reports the MSI capability on the
@@ -1136,7 +1139,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
if (INTEL_INFO(dev)->num_pipes) {
ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
if (ret)
- goto out_gem_unload;
+ goto out_cleanup_shrinker;
}
ret = i915_load_modeset_init(dev);
@@ -1174,7 +1177,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
out_power_well:
intel_power_domains_fini(dev_priv);
drm_vblank_cleanup(dev);
-out_gem_unload:
+out_cleanup_shrinker:
i915_gem_shrinker_cleanup(dev_priv);
if (dev->pdev->msi_enabled)
@@ -1190,9 +1193,9 @@ out_uncore_fini:
i915_mmio_cleanup(dev);
put_bridge:
pci_dev_put(dev_priv->bridge_dev);
- i915_gem_load_cleanup(dev);
out_runtime_pm_put:
intel_runtime_pm_put(dev_priv);
+ i915_gem_load_cleanup(dev);
i915_workqueues_cleanup(dev_priv);
out_free_priv:
kfree(dev_priv);
@@ -1277,8 +1280,8 @@ int i915_driver_unload(struct drm_device *dev)
intel_uncore_fini(dev);
i915_mmio_cleanup(dev);
- i915_gem_load_cleanup(dev);
pci_dev_put(dev_priv->bridge_dev);
+ i915_gem_load_cleanup(dev);
i915_workqueues_cleanup(dev_priv);
kfree(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1557d65..f62b6d1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2836,6 +2836,7 @@ int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
void i915_gem_load_init(struct drm_device *dev);
void i915_gem_load_cleanup(struct drm_device *dev);
+void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
void *i915_gem_object_alloc(struct drm_device *dev);
void i915_gem_object_free(struct drm_i915_gem_object *obj);
void i915_gem_object_init(struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b854af2..3dab0d6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5029,6 +5029,26 @@ init_ring_lists(struct intel_engine_cs *ring)
}
void
+i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
+{
+ if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
+ !IS_CHERRYVIEW(dev_priv))
+ dev_priv->num_fence_regs = 32;
+ else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) ||
+ IS_I945GM(dev_priv) || IS_G33(dev_priv))
+ dev_priv->num_fence_regs = 16;
+ else
+ dev_priv->num_fence_regs = 8;
+
+ if (intel_vgpu_active(dev_priv->dev))
+ dev_priv->num_fence_regs =
+ I915_READ(vgtif_reg(avail_rs.fence_num));
+
+ /* Initialize fence registers to zero */
+ i915_gem_restore_fences(dev_priv->dev);
+}
+
+void
i915_gem_load_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5067,17 +5087,6 @@ i915_gem_load_init(struct drm_device *dev)
dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
- if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
- dev_priv->num_fence_regs = 32;
- else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
- dev_priv->num_fence_regs = 16;
- else
- dev_priv->num_fence_regs = 8;
-
- if (intel_vgpu_active(dev))
- dev_priv->num_fence_regs =
- I915_READ(vgtif_reg(avail_rs.fence_num));
-
/*
* Set initial sequence number for requests.
* Using this number allows the wraparound to happen early,
@@ -5086,11 +5095,8 @@ i915_gem_load_init(struct drm_device *dev)
dev_priv->next_seqno = ((u32)~0 - 0x1100);
dev_priv->last_seqno = ((u32)~0 - 0x1101);
- /* Initialize fence registers to zero */
INIT_LIST_HEAD(&dev_priv->mm.fence_list);
- i915_gem_restore_fences(dev);
- i915_gem_detect_bit_6_swizzle(dev);
init_waitqueue_head(&dev_priv->pending_flip_queue);
dev_priv->mm.interruptible = true;
--
2.5.0
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