Partial port of a patch from Mika that modifies reset function to handle
per engine resets. A domain reset function is introduces which accepts a
mask of all domains to be reset. In case of per engine reset only single
engine domain is specified where as for legacy full gpu reset all engine
domains are specified.
This change also supports to reset GuC which is required for some of the WA
where fw load can fail and we retry after resetting GuC.
Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
Cc: Dave Gordon <david.s.gordon@xxxxxxxxx>
Signed-off-by: Arun Siluvery <arun.siluvery@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_uncore.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index d31447f..80e38d5 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1510,6 +1510,21 @@ static int ironlake_do_reset(struct drm_device *dev)
return 0;
}
+static int gen6_domain_reset(struct drm_i915_private *dev_priv,
+ u32 hw_domain_mask)
+{
+ int ret;
+
+ __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
+
+#define ACKED ((__raw_i915_read32(dev_priv, GEN6_GDRST) & hw_domain_mask) == 0)
+ /* Spin waiting for the device to ack the reset requests */
+ ret = wait_for_atomic_us(ACKED, 500);
+#undef ACKED
+
+ return ret;
+}
+
static int gen6_do_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
--
1.9.1
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