From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Read out the RPS frequencies already in intel_init_gt_powersave()
on all the platforms. So far we only did that on VLV/CHV, and the
rest of the platforms read them out at rps enable time, which happens
asynchronously from a workqueue. Reading them out earlier prevents
userspace from reading out invalid (zero) values via the relevant
sysfs files before the rps enable work has been executed.
This used to be prevented by the flush_delayed_work() + locking
in the sysfs code, but now that we no longer do that, we run the
risk of letting userspace see the initial zeroed values.
Note that it's still possible to read out cur_freq as 0, since that
only gets initialized from the delayed rps enable. Should that pose
a real problem, I guess we could always add the flush+locking back
for the cur_freq read.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_pm.c | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2591d533a895..5fe098b94f06 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4782,8 +4782,6 @@ static void gen9_enable_rps(struct drm_device *dev)
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
- gen6_init_rps_frequencies(dev);
-
/* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
@@ -4896,9 +4894,6 @@ static void gen8_enable_rps(struct drm_device *dev)
/* 2a: Disable RC states. */
I915_WRITE(GEN6_RC_CONTROL, 0);
- /* Initialize rps frequencies */
- gen6_init_rps_frequencies(dev);
-
/* 2b: Program RC6 thresholds.*/
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
@@ -4988,9 +4983,6 @@ static void gen6_enable_rps(struct drm_device *dev)
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
- /* Initialize rps frequencies */
- gen6_init_rps_frequencies(dev);
-
/* disable the counters and set deterministic thresholds */
I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -6197,6 +6189,8 @@ void intel_init_gt_powersave(struct drm_device *dev)
cherryview_init_gt_powersave(dev);
else if (IS_VALLEYVIEW(dev))
valleyview_init_gt_powersave(dev);
+ else if (INTEL_INFO(dev_priv)->gen >= 6)
+ gen6_init_rps_frequencies(dev);
}
void intel_cleanup_gt_powersave(struct drm_device *dev)
--
2.4.10
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