On ke, 2016-02-17 at 21:41 +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> LPT/WPT-H are limited to max 180 MHz CRT dotclock. Most other
> platforms
> have a limit of 350 MHz. Supposedly gen3 and gen4 go up to 400 MHz.
>
> VLV is a bit special since the docs are poor. Supposedly the DAC
> would be good up to 355 MHz, but currently we limit the DPLL to
> 270 MHz, so we'll have to limit the port clock to the same unless
> we change the DPLL limits.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_crt.c | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_crt.c
> b/drivers/gpu/drm/i915/intel_crt.c
> index 08964bbd7c82..6bdd4f4310f1 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -220,18 +220,26 @@ intel_crt_mode_valid(struct drm_connector
> *connector,
> {
> struct drm_device *dev = connector->dev;
> int max_dotclk = to_i915(dev)->max_dotclk_freq;
> + int max_clock;
>
> - int max_clock = 0;
> if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return MODE_NO_DBLESCAN;
>
> if (mode->clock < 25000)
> return MODE_CLOCK_LOW;
>
> - if (IS_GEN2(dev))
> - max_clock = 350000;
> - else
> + if (HAS_PCH_LPT(dev))
> + max_clock = 180000;
> + else if (IS_VALLEYVIEW(dev))
> + /*
> + * 270 MHz due to current DPLL limits,
> + * DAC limit supposedly 355 MHz.
> + */
> + max_clock = 270000;
> + else if (IS_GEN3(dev) || IS_GEN4(dev))
> max_clock = 400000;
> + else
> + max_clock = 350000;
> if (mode->clock > max_clock)
> return MODE_CLOCK_HIGH;
>
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