On Thu, 11 Feb 2016, Ramalingam C <ramalingam.c@xxxxxxxxx> wrote:
> From: Deepak M <m.deepak@xxxxxxxxx>
>
> The bpp value which is used while calulating the txbyteclkhs values
> should be wrt the pixel format value. Currently bpp is coming
> from pipe config to calculate txbyteclkhs. Fix it in this patch.
>
> V2: dsi_pixel_format_bpp is used to retrieve the bpp from pixel_format
> [Review: Jani]
>
> Signed-off-by: Deepak M <m.deepak@xxxxxxxxx>
> Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@xxxxxxxxx>
> Signed-off-by: Ramalingam C <ramalingam.c@xxxxxxxxx>
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
This needs a Tested-by on at least BYT to ensure everything still works.
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 5 ++---
> drivers/gpu/drm/i915/intel_dsi.h | 2 ++
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 5 +----
> drivers/gpu/drm/i915/intel_dsi_pll.c | 2 +-
> 4 files changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 91cef35..ce94342 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -775,10 +775,9 @@ static void set_dsi_timings(struct drm_encoder *encoder,
> {
> struct drm_device *dev = encoder->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> enum port port;
> - unsigned int bpp = intel_crtc->config->pipe_bpp;
> + unsigned int bpp = dsi_pixel_format_bpp(intel_dsi->pixel_format);
> unsigned int lane_count = intel_dsi->lane_count;
>
> u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
> @@ -849,7 +848,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
> enum port port;
> - unsigned int bpp = intel_crtc->config->pipe_bpp;
> + unsigned int bpp = dsi_pixel_format_bpp(intel_dsi->pixel_format);
> u32 val, tmp;
> u16 mode_hdisplay;
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index de7be7f..92f3922 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -34,6 +34,8 @@
> #define DSI_DUAL_LINK_FRONT_BACK 1
> #define DSI_DUAL_LINK_PIXEL_ALT 2
>
> +int dsi_pixel_format_bpp(int pixel_format);
> +
> struct intel_dsi_host;
>
> struct intel_dsi {
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 1d43e6f..23c0f67 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -420,10 +420,7 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
> intel_dsi->dual_link = mipi_config->dual_link;
> intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
>
> - if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
> - bits_per_pixel = 18;
> - else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
> - bits_per_pixel = 16;
> + bits_per_pixel = dsi_pixel_format_bpp(intel_dsi->pixel_format);
>
> intel_dsi->operation_mode = mipi_config->is_cmd_mode;
> intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index bb5e95a..70883c5 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -30,7 +30,7 @@
> #include "i915_drv.h"
> #include "intel_dsi.h"
>
> -static int dsi_pixel_format_bpp(int pixel_format)
> +int dsi_pixel_format_bpp(int pixel_format)
> {
> int bpp;
--
Jani Nikula, Intel Open Source Technology Center
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