From: Dave Gordon <david.s.gordon@xxxxxxxxx> Added an interface for user land applications/libraries/services to set their GPU scheduler priority. This extends the existing context parameter IOCTL interface to add a scheduler priority parameter. The range is +/-1023 with +ve numbers meaning higher priority. Only system processes may set a higher priority than the default (zero), normal applications may only lower theirs. v2: New patch in series. For: VIZ-1587 Signed-off-by: Dave Gordon <David.S.Gordon@xxxxxxxxx> Signed-off-by: John Harrison <John.C.Harrison@xxxxxxxxx> --- drivers/gpu/drm/i915/i915_drv.h | 14 ++++++++++++++ drivers/gpu/drm/i915/i915_gem_context.c | 24 ++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 +++ include/uapi/drm/i915_drm.h | 1 + 4 files changed, 42 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3f4c4f0..5d02f44 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -847,6 +847,19 @@ struct i915_ctx_hang_stats { bool banned; }; +/* + * User-settable GFX scheduler priorities are on a scale of -1023 (I don't + * care about running) to +1023 (I'm the most important thing in existence) + * with zero being the default. Any process may decrease its scheduling + * priority, but only a sufficiently privileged process may increase it + * beyond zero. + */ + +struct i915_ctx_sched_info { + /* Scheduling priority */ + int32_t priority; +}; + struct i915_fence_timeline { char name[32]; unsigned fence_context; @@ -887,6 +900,7 @@ struct intel_context { int flags; struct drm_i915_file_private *file_priv; struct i915_ctx_hang_stats hang_stats; + struct i915_ctx_sched_info sched_info; struct i915_hw_ppgtt *ppgtt; /* Legacy ring buffer submission */ diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 3dcb2f4..6ac03e8 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -956,6 +956,9 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, else args->value = to_i915(dev)->gtt.base.total; break; + case I915_CONTEXT_PARAM_PRIORITY: + args->value = (__u64) ctx->sched_info.priority; + break; default: ret = -EINVAL; break; @@ -993,6 +996,7 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, else ctx->hang_stats.ban_period_seconds = args->value; break; + case I915_CONTEXT_PARAM_NO_ZEROMAP: if (args->size) { ret = -EINVAL; @@ -1001,6 +1005,26 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0; } break; + + case I915_CONTEXT_PARAM_PRIORITY: + { + int32_t priority = (int32_t) args->value; + struct drm_i915_private *dev_priv = dev->dev_private; + struct i915_scheduler *scheduler = dev_priv->scheduler; + + if (args->size) + ret = -EINVAL; + else if ((priority > scheduler->priority_level_max) || + (priority < scheduler->priority_level_min)) + ret = -EINVAL; + else if ((priority > 0) && + !capable(CAP_SYS_ADMIN)) + ret = -EPERM; + else + ctx->sched_info.priority = priority; + break; + } + default: ret = -EINVAL; break; diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index a42a13e..793fbce 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1707,6 +1707,9 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, params->args_DR4 = args->DR4; params->batch_obj = batch_obj; + /* Start with the context's priority level */ + qe.priority = ctx->sched_info.priority; + /* * Save away the list of objects used by this batch buffer for the * purpose of tracking inter-buffer dependencies. diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index acf2102..8a01a47 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -1140,6 +1140,7 @@ struct drm_i915_gem_context_param { #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 +#define I915_CONTEXT_PARAM_PRIORITY 0x4 __u64 value; }; -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx