On ke, 2016-02-17 at 21:41 +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> On HSW/BDW ddi_pll_sel is the actual register value. Let's dump
> it in hex so that people migth actually understand what it says.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index afcabe455ad1..f0f88061a9e5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12220,7 +12220,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
> pipe_config->dpll_hw_state.cfgcr1,
> pipe_config->dpll_hw_state.cfgcr2);
> } else if (HAS_DDI(dev)) {
> - DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
> + DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
> pipe_config->ddi_pll_sel,
> pipe_config->dpll_hw_state.wrpll,
> pipe_config->dpll_hw_state.spll);
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