On Tue, Feb 16, 2016 at 07:53:45PM +0200, Ander Conselvan de Oliveira wrote:
> The wait for other gens was added in commit 564ed191f5d8 ("drm/i915:
> gmch: fix stuck primary plane due to memory self-refresh mode") since
> that's necessary when disabling cxsr. However, cxsr disabling was later
> moved to intel_pre_disable_primary() in commit 87d4300a7dbc ("drm/i915:
> Move intel_(pre_disable/post_enable)_primary to intel_display.c, and use
> it there.") and that function got its own vblank wait for cxsr in commit
> 262cd2e154c2 ("drm/i915: CHV DDR DVFS support and another watermark
> rewrite"). So remove the extra vblank wait from i9xx_crtc_distable().
>
> Cc: Kalyan Kondapally <kalyan.kondapally@xxxxxxxxx>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@xxxxxxxxx>
Reviewed-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 568eefc..3cb9383 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6317,10 +6317,9 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
> /*
> * On gen2 planes are double buffered but the pipe isn't, so we must
> * wait for planes to fully turn off before disabling the pipe.
> - * We also need to wait on all gmch platforms because of the
> - * self-refresh mode constraint explained above.
> */
> - intel_wait_for_vblank(dev, pipe);
> + if (IS_GEN2(dev))
> + intel_wait_for_vblank(dev, pipe);
>
> for_each_encoder_on_crtc(dev, crtc, encoder)
> encoder->disable(encoder);
> --
> 2.4.3
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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