On Tue, Feb 16, 2016 at 10:25:11AM +0100, Maarten Lankhorst wrote:
> The check for active_crtcs == 0 was performed by the callers, when changing
> the patches I forgot to remove those hunks.
>
> This resulted in skylake scalers still not having the correct cdclk to
> calculate scaling when all crtc's were dpms off.
>
> Fixes: 1a617b77658e ("drm/i915: Keep track of the cdclk as if all crtc's were active.")
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 12 ++++--------
> 1 file changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2cefd137c840..3934b4764815 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6039,8 +6039,7 @@ static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
> return 144000;
> }
>
> -/* Compute the max pixel clock for new configuration. Uses atomic state if
> - * that's non-NULL, look at current state otherwise. */
> +/* Compute the max pixel clock for new configuration. */
> static int intel_mode_max_pixclk(struct drm_device *dev,
> struct drm_atomic_state *state)
> {
> @@ -6063,9 +6062,6 @@ static int intel_mode_max_pixclk(struct drm_device *dev,
> intel_state->min_pixclk[i] = pixclk;
> }
>
> - if (!intel_state->active_crtcs)
> - return 0;
> -
> for_each_pipe(dev_priv, pipe)
> max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
>
> @@ -9677,9 +9673,6 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
> intel_state->min_pixclk[i] = pixel_rate;
> }
>
> - if (!intel_state->active_crtcs)
> - return 0;
> -
> for_each_pipe(dev_priv, pipe)
> max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
>
> @@ -13191,6 +13184,9 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
>
> if (ret < 0)
> return ret;
> +
> + DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
> + intel_state->cdclk, intel_state->dev_cdclk);
> } else
> to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
> --
> 2.1.0
>
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--
Ville Syrjälä
Intel OTC
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