Imre Deak <imre.deak@xxxxxxxxx> writes:
> The assumption when adding the intel_display_power_is_enabled() checks
> was that if it returns success the power can't be turned off afterwards
> during the HW access, which is guaranteed by modeset locks. This isn't
> always true, so make sure we hold a dedicated reference for the time of
> the access.
>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6abfc54..fe249ff 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13699,7 +13699,7 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
> {
> uint32_t val;
>
> - if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
> + if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
> return false;
>
> val = I915_READ(PCH_DPLL(pll->id));
> @@ -13707,6 +13707,8 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
> hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
> hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
>
> + intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
> +
> return val & DPLL_VCO_ENABLE;
> }
>
> --
> 2.5.0
>
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