On Thu, Feb 04, 2016 at 12:50:55PM +0200, Jani Nikula wrote:
> From: Deepak M <m.deepak@xxxxxxxxx>
>
> Make the gpio read/write functions more generic iosf sideband read/write
> functions, taking the iosf port as argument.
>
> v2: rebase
> v3: rebase
> v4 by Jani: address Ville's review
>
> Signed-off-by: Deepak M <m.deepak@xxxxxxxxx>
> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 5 +++--
> drivers/gpu/drm/i915/intel_sideband.c | 9 +++++----
> 4 files changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index af601be8b490..47da528c16d0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3475,8 +3475,8 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val
> u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
> void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
> u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
> -u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
> -void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> +u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
> +void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
> u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
> void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c761fa2f3b8b..d00e5b8e5469 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -618,6 +618,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define IOSF_PORT_CCK 0x14
> #define IOSF_PORT_DPIO_2 0x1a
> #define IOSF_PORT_FLISDSI 0x1b
> +#define IOSF_PORT_GPIO_SC 0x48
> +#define IOSF_PORT_GPIO_SUS 0xa8
> #define IOSF_PORT_CCU 0xa9
> #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
> #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 3e1e70f81506..de1966552a33 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -235,14 +235,15 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> if (!gtable[gpio].init) {
> /* program the function */
> /* FIXME: remove constant below */
> - vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
> + vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,
> + 0x2000CC00);
> gtable[gpio].init = 1;
> }
>
> val = 0x4 | action;
>
> /* pull up/down */
> - vlv_gpio_nc_write(dev_priv, pad, val);
> + vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
> mutex_unlock(&dev_priv->sb_lock);
>
> out:
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index f5b0ab6f5942..78c3d93fd963 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -129,17 +129,18 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
> return val;
> }
>
> -u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
> +u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg)
> {
> u32 val = 0;
> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
> + vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), port,
^
Not correct.
> SB_CRRDDA_NP, reg, &val);
> return val;
> }
>
> -void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> +void vlv_iosf_sb_write(struct drm_i915_private *dev_priv,
> + u8 port, u32 reg, u32 val)
> {
> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
> + vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), port,
ditto
> SB_CRWRDA_NP, reg, &val);
> }
>
> --
> 2.1.4
>
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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