On Fri, Jan 29, 2016 at 04:49:29PM +0200, Ville Syrjälä wrote:
> On Thu, Jan 28, 2016 at 03:09:37PM -0800, Matt Roper wrote:
> > In commit bfb9faab8 we added a workaround for some BXT BIOS that fail to
> > properly initialize the DDI_A_4_LANES bit of the control register (4
> > lanes is the only valid configuration on BXT since there is no DDI E to
> > share with). A recent patch added some additional checks on this
> > register bit before the workaround gets applied; this breaks eDP on BXT
> > in some settings. Some minor code shuffling is all we need to restore
> > the workaround.
> >
> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > Fixes: 7cd87cb80 ("drm/i915: Check max number of lanes when registering DDI ports")
> > Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 75b57a8..6ac80cd 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -3288,7 +3288,6 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
> > intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
> > (DDI_BUF_PORT_REVERSAL |
> > DDI_A_4_LANES);
> > - intel_dig_port->max_lanes = max_lanes;
> >
> > /*
> > * Bspec says that DDI_A_4_LANES is the only supported configuration
> > @@ -3301,9 +3300,12 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
> > if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> > DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
> > intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> > + max_lanes = 4;
> > }
> > }
> >
> > + intel_dig_port->max_lanes = max_lanes;
> > +
>
> Oops, my bad.
>
> Might be a bit nicer to really fixup the register value before
> determining max_lanes, but since there's no port E on BXT it doesn't
> really matter I suppose. So this fix should be fine as is.
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Pushed to dinq; thanks for the review.
Matt
>
> > intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
> > intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
> > intel_encoder->cloneable = 0;
> > --
> > 2.1.4
>
> --
> Ville Syrjälä
> Intel OTC
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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