On Tue, 02 Feb 2016, Lyude <cpaul@xxxxxxxxxx> wrote:
> We don't actually check for INTEL_OUTPUT_DP_MST at all in here, as a
> result we skip assigning a DPLL to any DP MST ports, which makes link
> training fail, after which things just keep going downhill from there.
Apparently broken since
commit 82d35437018950c25200051733fb2fbf63cca86c
Author: Satheeshakrishna M <satheeshakrishna.m@xxxxxxxxx>
Date: Thu Nov 13 14:55:20 2014 +0000
drm/i915/skl: Implementation of SKL DPLL programming
> Consequently, this fixes DisplayPort MST causing kernel panics, machine
> check errors, etc. on Skylake.
Please copy-paste some traces for the commit message so it'll be easier
to match bug reports and fixes later on.
BR,
Jani.
>
> Signed-off-by: Lyude <cpaul@xxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index e6408e5..54a165b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1589,7 +1589,8 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
> DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
> DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
> wrpll_params.central_freq;
> - } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
> + } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
> + intel_encoder->type == INTEL_OUTPUT_DP_MST) {
> switch (crtc_state->port_clock / 2) {
> case 81000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
--
Jani Nikula, Intel Open Source Technology Center
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