From: "Niu,Bing" <bing.niu@xxxxxxxxx>
This patch introduces vGPU MMIO register emulation core logics.
Under virtualization environment, all GEN MMIO register access will be trapped
by hypervisor and forwarded to GVT-g. GVT-g will handle these MMIO register
emulation request by different policies.
For some kinds of virtual registers, accessing one or more bit may cause other
bit changes, a mmio emulation read/write handler will be called when GVT-g is
handling the emulation request.
Signed-off-by: Niu,Bing <bing.niu@xxxxxxxxx>
---
drivers/gpu/drm/i915/gvt/debug.h | 16 +
drivers/gpu/drm/i915/gvt/gvt.c | 18 +-
drivers/gpu/drm/i915/gvt/gvt.h | 83 ++-
drivers/gpu/drm/i915/gvt/handlers.c | 1098 +++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/gvt/instance.c | 2 +
drivers/gpu/drm/i915/gvt/interrupt.h | 14 +
drivers/gpu/drm/i915/gvt/mmio.c | 33 +-
drivers/gpu/drm/i915/gvt/mmio.h | 16 +-
drivers/gpu/drm/i915/gvt/reg.h | 374 ++++++++++++
9 files changed, 1631 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/debug.h b/drivers/gpu/drm/i915/gvt/debug.h
index 18e1467..807d9e8 100644
--- a/drivers/gpu/drm/i915/gvt/debug.h
+++ b/drivers/gpu/drm/i915/gvt/debug.h
@@ -40,6 +40,19 @@
} \
} while (0);
+#define ASSERT_VM(x, vgt) \
+ do { \
+ if (!(x)) { \
+ printk("Assert at %s line %d\n", \
+ __FILE__, __LINE__); \
+ if (atomic_cmpxchg(&(vgt)->crashing, 0, 1)) \
+ break; \
+ gvt_warn("Killing VM%d", (vgt)->vm_id); \
+ if (!hypervisor_pause_domain((vgt))) \
+ hypervisor_shutdown_domain((vgt)); \
+ } \
+ } while (0)
+
#define gvt_info(fmt, args...) \
printk(KERN_INFO"[GVT-g] "fmt"\n", ##args)
@@ -58,6 +71,9 @@ enum {
GVT_DBG_CORE = (1 << 0),
GVT_DBG_MM = (1 << 1),
GVT_DBG_IRQ = (1 << 2),
+ GVT_DBG_DPY = (1 << 3),
+ GVT_DBG_RENDER = (1 << 4),
+ GVT_DBG_EDID = (1 << 5)
};
#define gvt_dbg_core(fmt, args...) \
diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
index 63eb02c..84549a0 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.c
+++ b/drivers/gpu/drm/i915/gvt/gvt.c
@@ -169,6 +169,11 @@ static void clean_initial_mmio_state(struct pgt_device *pdev)
iounmap(pdev->gmadr_va);
pdev->gmadr_va = NULL;
}
+
+ if(pdev->reg_info) {
+ vfree(pdev->reg_info);
+ pdev->reg_info = NULL;
+ }
}
static bool init_initial_mmio_state(struct pgt_device *pdev)
@@ -197,6 +202,12 @@ static bool init_initial_mmio_state(struct pgt_device *pdev)
goto err;
}
+ pdev->reg_info = vzalloc(pdev->reg_num * sizeof(u32));
+ if (!pdev->reg_info) {
+ printk("vGT: failed to allocate reg_info\n");
+ goto err;
+ }
+
gvt_info("bar0: 0x%llx, bar1: 0x%llx", bar0, bar1);
gvt_info("mmio size: %x", pdev->mmio_size);
gvt_info("gttmmio: 0x%llx, gmadr: 0x%llx", pdev->gttmmio_base, pdev->gmadr_base);
@@ -226,6 +237,12 @@ static int gvt_service_thread(void *data)
if (kthread_should_stop())
break;
+ if (test_and_clear_bit(GVT_REQUEST_UEVENT,
+ (void *)&pdev->service_request)) {
+ gvt_dpy_ready_uevent_handler(pdev);
+ }
+
+
if (r) {
gvt_warn("service thread is waken up by unexpected signal.");
continue;
@@ -340,7 +357,6 @@ static struct pgt_device *alloc_pgt_device(struct drm_i915_private *dev_priv)
mutex_init(&pdev->lock);
pdev->dev_priv = dev_priv;
idr_init(&pdev->instance_idr);
-
return pdev;
err:
free_pgt_device(pdev);
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 456b332..62cbb62 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -28,6 +28,7 @@
#include "i915_vgpu.h"
#include "debug.h"
+
#include "params.h"
#include "reg.h"
#include "hypercall.h"
@@ -129,18 +130,23 @@ struct gvt_virtual_device_state {
struct gvt_virtual_opregion_state opregion;
};
+struct gvt_uevent {
+ int vm_id;
+};
+
struct vgt_device {
int id;
int vm_id;
struct pgt_device *pdev;
- bool warn_untrack;
atomic_t active;
struct gvt_virtual_device_state state;
struct gvt_statistics stat;
struct gvt_vgtt_info gtt;
void *hypervisor_data;
unsigned long low_mem_max_gpfn;
+ unsigned long last_reset_time;
atomic_t crashing;
+ bool warn_untrack;
};
struct gvt_gm_allocator {
@@ -156,6 +162,7 @@ struct pgt_device {
struct idr instance_idr;
struct gvt_device_info device_info;
+ struct gvt_uevent uevent;
u8 initial_cfg_space[GVT_CFG_SPACE_SZ];
u64 bar_size[GVT_BAR_NUM];
@@ -200,6 +207,32 @@ struct pgt_device {
struct gvt_gtt_info gtt;
};
+/* request types to wake up main thread */
+#define GVT_REQUEST_IRQ 0 /* a new irq pending from device */
+#define GVT_REQUEST_UEVENT 1
+#define GVT_REQUEST_CTX_SWITCH 2 /* immediate reschedule(context switch) requested */
+#define GVT_REQUEST_EMUL_DPY_EVENTS 3
+#define GVT_REQUEST_DEVICE_RESET 4
+#define GVT_REQUEST_SCHED 5
+#define GVT_REQUEST_CTX_EMULATION_RCS 6 /* Emulate context switch irq of Gen8 */
+#define GVT_REQUEST_CTX_EMULATION_VCS 7 /* Emulate context switch irq of Gen8 */
+#define GVT_REQUEST_CTX_EMULATION_BCS 8 /* Emulate context switch irq of Gen8 */
+#define GVT_REQUEST_CTX_EMULATION_VECS 9 /* Emulate context switch irq of Gen8 */
+#define GVT_REQUEST_CTX_EMULATION_VCS2 10 /* Emulate context switch irq of Gen8 */
+
+static inline void gvt_raise_request(struct pgt_device *pdev, uint32_t flag)
+{
+ set_bit(flag, (void *)&pdev->service_request);
+ if (waitqueue_active(&pdev->service_thread_wq))
+ wake_up(&pdev->service_thread_wq);
+}
+
+static inline bool vgt_chk_raised_request(struct pgt_device *pdev, uint32_t flag)
+{
+ return !!(test_bit(flag, (void *)&pdev->service_request));
+}
+
+
/* definitions for physical aperture/GM space */
#define phys_aperture_sz(pdev) (pdev->bar_size[1])
#define phys_aperture_pages(pdev) (phys_aperture_sz(pdev) >> GTT_PAGE_SHIFT)
@@ -266,22 +299,12 @@ extern void gvt_free_gm_and_fence_resource(struct vgt_device *vgt);
#define REG_INDEX(reg) ((reg) >> 2)
-#define D_SNB (1 << 0)
-#define D_IVB (1 << 1)
-#define D_HSW (1 << 2)
-#define D_BDW (1 << 3)
+#define D_HSW (1 << 0)
+#define D_BDW (1 << 1)
#define D_GEN8PLUS (D_BDW)
-#define D_GEN75PLUS (D_HSW | D_BDW)
-#define D_GEN7PLUS (D_IVB | D_HSW | D_BDW)
-
#define D_BDW_PLUS (D_BDW)
-#define D_HSW_PLUS (D_HSW | D_BDW)
-#define D_IVB_PLUS (D_IVB | D_HSW | D_BDW)
-
-#define D_PRE_BDW (D_SNB | D_IVB | D_HSW)
-
-#define D_ALL (D_SNB | D_IVB | D_HSW | D_BDW)
+#define D_ALL (D_HSW | D_BDW)
#define reg_addr_fix(pdev, reg) (pdev->reg_info[REG_INDEX(reg)] & GVT_REG_ADDR_FIX)
#define reg_hw_status(pdev, reg) (pdev->reg_info[REG_INDEX(reg)] & GVT_REG_HW_STATUS)
@@ -421,6 +444,29 @@ static inline void gvt_mmio_posting_read(struct pgt_device *pdev, u32 reg)
POSTING_READ(tmp);
}
+static inline void gvt_set_dpy_uevent(struct vgt_device *vgt)
+{
+ struct gvt_uevent *event = &vgt->pdev->uevent;
+
+ event->vm_id = vgt->vm_id;
+}
+
+static inline bool gvt_dpy_ready_uevent_handler(struct pgt_device *pdev)
+{
+ int retval;
+ struct kobject *kobj = &(pdev->dev_priv->dev->primary->kdev->kobj);
+ char *env[3] = {"VGT_DISPLAY_READY=1", NULL, NULL};
+ char vmid_str[20];
+ snprintf(vmid_str, 20, "VMID=%d", pdev->uevent.vm_id);
+ env[1] = vmid_str;
+
+ retval = kobject_uevent_env(kobj, KOBJ_ADD, env);
+ if (retval == 0)
+ return true;
+ else
+ return false;
+}
+
extern void gvt_clean_initial_mmio_state(struct pgt_device *pdev);
extern bool gvt_setup_initial_mmio_state(struct pgt_device *pdev);
@@ -618,9 +664,18 @@ static inline u32 h2g_gtt_index(struct vgt_device *vgt, uint32_t h_index)
/* get one bit of the data, bit is starting from zeor */
#define GVT_GET_BIT(data, bit) GVT_GET_BITS(data, bit, bit)
+int gvt_render_mmio_to_ring_id(unsigned int reg);
+int gvt_ring_id_to_render_mmio_base(int ring_id);
+
int gvt_hvm_map_aperture(struct vgt_device *vgt, int map);
int gvt_hvm_set_trap_area(struct vgt_device *vgt, int map);
+bool gvt_default_mmio_read(struct vgt_device *vgt, unsigned int offset, void *p_data, unsigned int bytes);
+bool gvt_default_mmio_write(struct vgt_device *vgt, unsigned int offset, void *p_data, unsigned int bytes);
+
+bool register_mmio_handler(struct pgt_device *pdev, unsigned int start, int bytes,
+ gvt_mmio_handler_t read, gvt_mmio_handler_t write);
+
#include "mpt.h"
#endif
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index a6ec4f3..ba29c9c 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -23,18 +23,1107 @@
#include "gvt.h"
-/* TODO: Merge register definition from i915. */
+static bool mmio_not_allow_read(struct vgt_device *vgt, unsigned int offset,
+ void *p_data, unsigned int bytes)
+{
+ gvt_err("[vgt %d]: reading MMIO reg 0x%x is not allowed.", vgt->id, offset);
+ memset(p_data, 0, bytes);
+ return true;
+}
+
+static bool mmio_not_allow_write(struct vgt_device *vgt,
+ unsigned int offset, void *p_data, unsigned int bytes)
+{
+ gvt_err("[vgt %d]: writing MMIO reg 0x%x is not allowed.",
+ vgt->id, offset);
+ return true;
+}
+
+/* Fence MMIO handlers. */
+static bool check_fence_mmio_access(struct vgt_device *vgt,
+ unsigned int off, void *p_data, unsigned int bytes)
+{
+ unsigned long fence_num;
+
+ ASSERT(off >= i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)) &&
+ off <= i915_mmio_reg_offset(FENCE_REG_GEN6_HI(GVT_MAX_NUM_FENCES)));
+
+ if (bytes > 8 && (off & (bytes - 1))) {
+ gvt_err("[vgt %d] unsupported access pattern, off %x bytes %x",
+ vgt->id, off, bytes);
+ return false;
+ }
+
+ fence_num = (off - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3;
+
+ if (fence_num >= vgt->state.gm.fence_sz)
+ gvt_warn("[vgt %d] access unassigned fence reg %x, total: %x",
+ vgt->id, off, vgt->state.gm.fence_sz);
+ return true;
+}
+
+static bool fence_mmio_read(struct vgt_device *vgt, unsigned int off,
+ void *p_data, unsigned int bytes)
+{
+ if (!check_fence_mmio_access(vgt, off, p_data, bytes))
+ return false;
+
+ return gvt_default_mmio_read(vgt, off, p_data, bytes);
+}
+
+static bool fence_mmio_write(struct vgt_device *vgt, unsigned int off,
+ void *p_data, unsigned int bytes)
+{
+ if (!check_fence_mmio_access(vgt, off, p_data, bytes))
+ return false;
+
+ if (!gvt_default_mmio_write(vgt, off, p_data, bytes))
+ return false;
+
+ /* TODO: Check address space */
+
+ /* FENCE registers are physically assigned, update! */
+ if (bytes < 8)
+ gvt_mmio_write(vgt->pdev, off + vgt->state.gm.fence_base * 8,
+ __sreg(vgt, off));
+ else
+ gvt_mmio_write64(vgt->pdev, off + vgt->state.gm.fence_base * 8,
+ __sreg64(vgt, off));
+ return true;
+}
+
+static bool mt_force_wake_write(struct vgt_device *vgt, unsigned int offset,
+ void *p_data, unsigned int bytes)
+{
+ u32 data, mask, wake, old_wake, new_wake;
+
+ data = *(u32*) p_data;
+
+ /* bit 16-31: mask
+ bit 0-15: force wake
+ forcewake bit apply only if its mask bit is 1
+ */
+ mask = data >> 16;
+ wake = data & 0xFFFF;
+ old_wake = __vreg(vgt, _FORCEWAKE_MT) & 0xFFFF;
+
+ new_wake = (old_wake & ~mask) + (wake & mask);
+ __vreg(vgt, _FORCEWAKE_MT) = (data & 0xFFFF0000) + new_wake;
+ __vreg(vgt, _FORCEWAKE_ACK_HSW) = new_wake;
+
+ return true;
+}
+
+static bool gdrst_mmio_write(struct vgt_device *vgt, unsigned int offset,
+ void *p_data, unsigned int bytes)
+{
+ u32 data = *(u32 *)p_data;
+
+ if (data & GEN6_GRDOM_FULL) {
+ gvt_info("VM %d request Full GPU Reset\n", vgt->vm_id);
+ }
+
+ if (data & GEN6_GRDOM_RENDER) {
+ gvt_info("VM %d request GPU Render Reset\n", vgt->vm_id);
+ }
+
+ if (data & GEN6_GRDOM_MEDIA) {
+ gvt_info("VM %d request GPU Media Reset\n", vgt->vm_id);
+ }
+
+ if (data & GEN6_GRDOM_BLT) {
+ gvt_info("VM %d request GPU BLT Reset\n", vgt->vm_id);
+ }
+
+ return true;
+}
+
+static bool ring_mode_write(struct vgt_device *vgt, unsigned int off,
+ void *p_data, unsigned int bytes)
+{
+ return true;
+}
+
+static bool pvinfo_read(struct vgt_device *vgt, unsigned int offset,
+ void *p_data, unsigned int bytes)
+{
+ bool rc = gvt_default_mmio_read(vgt, offset, p_data, bytes);
+ bool invalid_read = false;
+
+ switch (offset) {
+ case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
+ if (offset + bytes > _vgtif_reg(vgt_id) + 4)
+ invalid_read = true;
+ break;
+
+ case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
+ _vgtif_reg(avail_rs.fence_num):
+ if (offset + bytes >
+ _vgtif_reg(avail_rs.fence_num) + 4)
+ invalid_read = true;
+ break;
+
+ case _vgtif_reg(drv_version_major) ...
+ _vgtif_reg(min_fence_num):
+ if (offset + bytes > _vgtif_reg(min_fence_num) + 4)
+ invalid_read = true;
+ break;
+ case _vgtif_reg(v2g_notify):
+ /* set cursor setting here. For example:
+ * *((unsigned int *)p_data)) = VGT_V2G_SET_SW_CURSOR;
+ */
+ break;
+ case _vgtif_reg(vgt_caps):
+ break;
+ default:
+ invalid_read = true;
+ break;
+ }
+
+ if (invalid_read)
+ gvt_warn("invalid pvinfo read: [%x:%x] = %x!!!\n",
+ offset, bytes, *(u32 *)p_data);
+
+ return rc;
+}
+
+static bool pvinfo_write(struct vgt_device *vgt, unsigned int offset,
+ void *p_data, unsigned int bytes)
+{
+ u32 val = *(u32 *)p_data;
+ u32 min;
+ bool rc = true;
+
+ switch (offset) {
+ case _vgtif_reg(min_low_gmadr):
+ min = val;
+ if (vgt->state.gm.aperture_sz < min) {
+ gvt_err("VM(%d): aperture size(%llx) is less than"
+ "its driver's minimum requirement(%x)!\n",
+ vgt->vm_id, vgt->state.gm.aperture_sz, min);
+ rc = false;
+ }
+ break;
+ case _vgtif_reg(min_high_gmadr):
+ min = val;
+ if (vgt->state.gm.gm_sz - vgt->state.gm.aperture_sz < min) {
+ gvt_err("VM(%d): hiden gm size(%llx) is less than"
+ "its driver's minimum requirement(%x)!\n",
+ vgt->vm_id, vgt->state.gm.gm_sz - vgt->state.gm.aperture_sz,
+ min);
+ rc = false;
+ }
+ break;
+ case _vgtif_reg(min_fence_num):
+ min = val;
+ if (vgt->state.gm.fence_sz < min) {
+ gvt_err("VM(%d): fence size(%x) is less than"
+ "its drivers minimum requirement(%x)!\n",
+ vgt->vm_id, vgt->state.gm.fence_sz, min);
+ rc = false;
+ }
+ break;
+ case _vgtif_reg(g2v_notify):
+ if (val == VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE) {
+ rc = gvt_g2v_create_ppgtt_mm(vgt, 3);
+ } else if (val == VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY) {
+ rc = gvt_g2v_destroy_ppgtt_mm(vgt, 3);
+ } else if (val == VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE) {
+ rc = gvt_g2v_create_ppgtt_mm(vgt, 4);
+ } else if (val == VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY) {
+ rc = gvt_g2v_destroy_ppgtt_mm(vgt, 4);
+ } else {
+ gvt_warn("Invalid PV notification. %x\n", val);
+ }
+ break;
+ case _vgtif_reg(pdp[0].lo):
+ case _vgtif_reg(pdp[0].hi):
+ case _vgtif_reg(pdp[1].lo):
+ case _vgtif_reg(pdp[1].hi):
+ case _vgtif_reg(pdp[2].lo):
+ case _vgtif_reg(pdp[2].hi):
+ case _vgtif_reg(pdp[3].lo):
+ case _vgtif_reg(pdp[3].hi):
+ case _vgtif_reg(execlist_context_descriptor_lo):
+ case _vgtif_reg(execlist_context_descriptor_hi):
+ break;
+
+ default:
+ /* keep rc's default value: true.
+ * NOTE: returning false will crash the VM.
+ */
+ gvt_warn("invalid pvinfo write: [%x:%x] = %x!!!\n",
+ offset, bytes, val);
+ break;
+ }
+
+ if (rc == true)
+ rc = gvt_default_mmio_write(vgt, offset, p_data, bytes);
+ return rc;
+}
+
+bool fpga_dbg_write(struct vgt_device *vgt, unsigned int reg,
+ void *p_data, unsigned int bytes)
+{
+ u32 v = *(u32 *)p_data;
+
+ if (v & FPGA_DBG_RM_NOCLAIM)
+ v &= ~ FPGA_DBG_RM_NOCLAIM;
+
+ return gvt_default_mmio_write(vgt, reg, &v, bytes);
+}
+
struct gvt_reg_info gvt_general_reg_info[] = {
-{0, 0, 0, 0, 0, NULL, NULL},
+ /* Interrupt registers - GT */
+ {_RING_IMR(RENDER_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, gvt_reg_imr_handler},
+ {_RING_IMR(BLT_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, gvt_reg_imr_handler},
+ {_RING_IMR(GEN6_BSD_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, gvt_reg_imr_handler},
+ {_RING_IMR(VEBOX_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, gvt_reg_imr_handler},
+
+ /* Interrupt registers - PCH */
+ {_SDEIMR, 4, F_VIRT, 0, D_ALL, NULL, gvt_reg_imr_handler},
+ {_SDEIER, 4, F_VIRT, 0, D_ALL, NULL, gvt_reg_ier_handler},
+ {_SDEIIR, 4, F_VIRT, 0, D_ALL, NULL, gvt_reg_iir_handler},
+ {_SDEISR, 4, F_VIRT, 0, D_ALL, NULL, gvt_reg_isr_write},
+
+ /* -------render regs---------- */
+ {_RING_HWSTAM(RENDER_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_RING_HWSTAM(BLT_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_RING_HWSTAM(GEN6_BSD_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_RING_HWSTAM(VEBOX_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+
+ {_RENDER_HWS_PGA_GEN7, 4, F_RDR_ADRFIX, 0xFFFFF000, D_ALL, NULL, NULL},
+ {_BSD_HWS_PGA_GEN7, 4, F_RDR_ADRFIX, 0xFFFFF000, D_ALL, NULL, NULL},
+ {_BLT_HWS_PGA_GEN7, 4, F_RDR_ADRFIX, 0xFFFFF000, D_ALL, NULL, NULL},
+ {_VEBOX_HWS_PGA_GEN7, 4, F_RDR_ADRFIX, 0xFFFFF000, D_ALL, NULL, NULL},
+
+ /* maybe an error in Linux driver. meant for VCS_HWS_PGA */
+ {_REG_RCS_EXCC, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_REG_VCS_EXCC, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_REG_BCS_EXCC, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_REG_RCS_UHPTR, 4, F_RDR_HWSTS, 0, D_ALL, NULL, NULL},
+ {_REG_VCS_UHPTR, 4, F_RDR_HWSTS, 0, D_ALL, NULL, NULL},
+ {_REG_BCS_UHPTR, 4, F_RDR_HWSTS, 0, D_ALL, NULL, NULL},
+ {_REG_VECS_UHPTR, 4, F_RDR_HWSTS, 0, D_ALL, NULL, NULL},
+ {_REG_RCS_BB_PREEMPT_ADDR, 4, F_RDR_ADRFIX, 0xFFFFF000, D_ALL, NULL, NULL},
+
+ {0x12198, 4, F_RDR_ADRFIX, 0xFFFFF000, D_ALL, NULL, NULL},
+
+ {_RING_TAIL(RENDER_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_RING_HEAD(RENDER_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_RING_START(RENDER_RING_BASE), 4, F_RDR_ADRFIX, 0xFFFFF000, D_ALL,
+ NULL, NULL},
+ {_RING_CTL(RENDER_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_RING_ACTHD(RENDER_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+
+ {_RING_TAIL(GEN6_BSD_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_RING_HEAD(GEN6_BSD_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_RING_START(GEN6_BSD_RING_BASE), 4, F_RDR_ADRFIX, 0xFFFFF000, D_ALL,
+ NULL, NULL},
+ {_RING_CTL(GEN6_BSD_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_RING_ACTHD(GEN6_BSD_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+
+ {_RING_TAIL(BLT_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_RING_HEAD(BLT_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_RING_START(BLT_RING_BASE), 4, F_RDR_ADRFIX, 0xFFFFF000, D_ALL,
+ NULL, NULL},
+ {_RING_CTL(BLT_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_RING_ACTHD(BLT_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+
+ {_RING_TAIL(VEBOX_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_RING_HEAD(VEBOX_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_RING_START(VEBOX_RING_BASE), 4, F_RDR_ADRFIX, 0xFFFFF000, D_ALL,
+ NULL, NULL},
+ {_RING_CTL(VEBOX_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_RING_ACTHD(VEBOX_RING_BASE), 4, F_RDR, 0, D_ALL, NULL, NULL},
+
+ {GVT_RING_MODE(RENDER_RING_BASE), 4, F_RDR_MODE, 0, D_ALL, NULL, ring_mode_write},
+ {GVT_RING_MODE(BLT_RING_BASE), 4, F_RDR_MODE, 0, D_ALL, NULL, ring_mode_write},
+ {GVT_RING_MODE(GEN6_BSD_RING_BASE), 4, F_RDR_MODE, 0, D_ALL, NULL, ring_mode_write},
+ {GVT_RING_MODE(VEBOX_RING_BASE), 4, F_RDR_MODE, 0, D_ALL, NULL, ring_mode_write},
+
+ {_RING_MI_MODE(RENDER_RING_BASE), 4, F_RDR_MODE, 0, D_ALL, NULL, NULL},
+ {_RING_MI_MODE(BLT_RING_BASE), 4, F_RDR_MODE, 0, D_ALL, NULL, NULL},
+ {_RING_MI_MODE(GEN6_BSD_RING_BASE), 4, F_RDR_MODE, 0, D_ALL, NULL, NULL},
+ {_RING_MI_MODE(VEBOX_RING_BASE), 4, F_RDR_MODE, 0, D_ALL, NULL, NULL},
+
+ {_RING_INSTPM(RENDER_RING_BASE), 4, F_RDR_MODE, 0, D_ALL, NULL, NULL},
+ {_RING_INSTPM(BLT_RING_BASE), 4, F_RDR_MODE, 0, D_ALL, NULL, NULL},
+ {_RING_INSTPM(GEN6_BSD_RING_BASE), 4, F_RDR_MODE, 0, D_ALL, NULL, NULL},
+ {_RING_INSTPM(VEBOX_RING_BASE), 4, F_RDR_MODE, 0, D_ALL, NULL, NULL},
+
+ {_GEN7_GT_MODE, 4, F_RDR_MODE, 0, D_ALL, NULL, NULL},
+ {_CACHE_MODE_0_GEN7, 4, F_RDR_MODE, 0, D_ALL, NULL, NULL},
+ {_CACHE_MODE_1, 4, F_RDR_MODE, 0, D_ALL, NULL, NULL},
+ {_REG_RCS_BB_ADDR, 4, F_RDR_ADRFIX, 0xFFFFF000, D_ALL, NULL, NULL},
+ {_REG_VCS_BB_ADDR, 4, F_RDR_ADRFIX, 0xFFFFF000, D_ALL, NULL, NULL},
+ {_REG_BCS_BB_ADDR, 4, F_RDR_ADRFIX, 0xFFFFF000, D_ALL, NULL, NULL},
+ {_REG_VECS_BB_ADDR, 4, F_RDR_ADRFIX, 0xFFFFF000, D_ALL, NULL, NULL},
+
+ {0x2050, 4, F_PT, 0, D_ALL, NULL, NULL},
+ {0x12050, 4, F_PT, 0, D_ALL, NULL, NULL},
+ {0x22050, 4, F_PT, 0, D_ALL, NULL, NULL},
+ {0x1A050, 4, F_PT, 0, D_ALL, NULL, NULL},
+
+ {0x20dc, 4, F_RDR_MODE, 0, D_ALL, NULL, NULL},
+ {__3D_CHICKEN3, 4, F_RDR_MODE, 0, D_ALL, NULL, NULL},
+ {0x2088, 4, F_RDR_MODE, 0, D_ALL, NULL, NULL},
+ {0x20e4, 4, F_RDR_MODE, 0, D_ALL, NULL, NULL},
+ {_REG_VFSKPD, 4, F_RDR_MODE, 0, D_ALL, NULL, NULL},
+ {_GAM_ECOCHK, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_GEN7_COMMON_SLICE_CHICKEN1, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_COMMON_SLICE_CHICKEN2, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {0x9030, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {0x20a0, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_REG_RCS_TIMESTAMP, 8, F_PT, 0, D_ALL, NULL, NULL},
+ {_REG_VCS_TIMESTAMP, 8, F_PT, 0, D_ALL, NULL, NULL},
+ {0x1a358, 8, F_PT, 0, D_ALL, NULL, NULL},
+ {_REG_BCS_TIMESTAMP, 8, F_PT, 0, D_ALL, NULL, NULL},
+ {0x2420, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {0x2430, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {0x2434, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {0x2438, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {0x243c, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {0x7018, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {0xe184, 4, F_RDR, 0, D_ALL, NULL, NULL},
+
+ /* -------display regs---------- */
+ {0x60220, 0x20, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x602a0, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {0x65050, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x650b4, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {VGA_CR_INDEX_MDA, 1, F_DPY, 0, D_ALL, NULL, NULL},
+ {VGA_ST01_MDA, 1, F_DPY, 0, D_ALL, NULL, NULL},
+ {VGA_AR_INDEX, 1, F_DPY, 0, D_ALL, NULL, NULL},
+ {VGA_DACMASK, 1, F_DPY, 0, D_ALL, NULL, NULL},
+ {VGA_MSR_READ, 1, F_DPY, 0, D_ALL, NULL, NULL},
+ {_VGA0, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_VGA1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_VGA_PD, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {0x42080, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {0xc4040, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+
+ {_DERRMR, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+
+ {GVT_CURSURF(PIPE_A), 4, F_DPY_ADRFIX, 0xFFFFF000, D_ALL, NULL, NULL},
+ {GVT_CURCNTR(PIPE_A), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_CURPOS(PIPE_A), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_CURSURFLIVE(PIPE_A), 4, F_DPY_HWSTS_ADRFIX, 0xFFFFF000, D_ALL, NULL,
+ mmio_not_allow_write},
+
+ {GVT_CURSURF(PIPE_B), 4, F_DPY_ADRFIX, 0xFFFFF000, D_ALL, NULL, NULL},
+ {GVT_CURCNTR(PIPE_B), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_CURPOS(PIPE_B), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_CURSURFLIVE(PIPE_B), 4, F_DPY_HWSTS_ADRFIX, 0xFFFFF000, D_ALL, NULL,
+ mmio_not_allow_write},
+
+ {GVT_CURSURF(PIPE_C), 4, F_DPY_ADRFIX, 0xFFFFF000, D_ALL, NULL, NULL},
+ {GVT_CURCNTR(PIPE_C), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_CURPOS(PIPE_C), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_CURSURFLIVE(PIPE_C), 4, F_DPY_HWSTS_ADRFIX, 0xFFFFF000, D_ALL, NULL,
+ mmio_not_allow_write},
+
+ {_REG_CURAPALET_0, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_CURAPALET_1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_CURAPALET_2, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_CURAPALET_3, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_LGC_PALETTE_A, 4 * 256, F_DPY, 0, D_ALL, NULL, NULL},
+ {_LGC_PALETTE_B, 4 * 256, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_LGC_PALETTE_C, 4 * 256, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {0x701b0, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+
+ {GVT_HTOTAL(PIPE_A), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_HBLANK(PIPE_A), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_HSYNC(PIPE_A), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_VTOTAL(PIPE_A), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_VBLANK(PIPE_A), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_VSYNC(PIPE_A), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_PIPESRC(PIPE_A), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_BCLRPAT(PIPE_A), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_VSYNCSHIFT(PIPE_A), 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {GVT_HTOTAL(PIPE_B), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_HBLANK(PIPE_B), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_HSYNC(PIPE_B), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_VTOTAL(PIPE_B), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_VBLANK(PIPE_B), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_VSYNC(PIPE_B), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_PIPESRC(PIPE_B), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_BCLRPAT(PIPE_B), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_VSYNCSHIFT(PIPE_B), 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {GVT_HTOTAL(PIPE_C), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_HBLANK(PIPE_C), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_HSYNC(PIPE_C), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_VTOTAL(PIPE_C), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_VBLANK(PIPE_C), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_VSYNC(PIPE_C), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_PIPESRC(PIPE_C), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_BCLRPAT(PIPE_C), 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {GVT_VSYNCSHIFT(PIPE_C), 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {0x6F000, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x6F004, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x6F008, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x6F00C, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x6F010, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x6F014, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x6F028, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x6F030, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x6F034, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x6F040, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x6F044, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_PIPEA_DATA_M1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PIPEA_DATA_N1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PIPEA_LINK_M1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PIPEA_LINK_N1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_PIPEB_DATA_M1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PIPEB_DATA_N1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PIPEB_LINK_M1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PIPEB_LINK_N1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_REG_PIPEC_DATA_M1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_PIPEC_DATA_N1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_PIPEC_LINK_M1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_PIPEC_LINK_N1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_PFA_CTL_1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PFA_WIN_SZ, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PFA_WIN_POS, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PFB_CTL_1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PFB_WIN_SZ, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PFB_WIN_POS, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_PF_CTL_2, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_PF_WIN_SZ_2, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_PF_WIN_POS_2, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_WM0_PIPEA_ILK, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_WM0_PIPEB_ILK, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_WM0_PIPEC_IVB, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_WM1_LP_ILK, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_WM2_LP_ILK, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_WM3_LP_ILK, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_WM1S_LP_ILK, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_WM2S_LP_IVB, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_WM3S_LP_IVB, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_REG_HISTOGRAM_THRSH, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_BLC_PWM_CPU_CTL2, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_BLC_PWM_CPU_CTL, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_BLC_PWM_PCH_CTL1, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_BLC_PWM_PCH_CTL2, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+
+ {_PCH_TRANS_HTOTAL_A, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANS_HBLANK_A, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANS_HSYNC_A, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANS_VTOTAL_A, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANS_VBLANK_A, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANS_VSYNC_A, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANS_VSYNCSHIFT_A, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_PCH_TRANS_HTOTAL_B, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANS_HBLANK_B, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANS_HSYNC_B, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANS_VTOTAL_B, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANS_VBLANK_B, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANS_VSYNC_B, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANS_VSYNCSHIFT_B, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_PCH_TRANSA_DATA_M1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANSA_DATA_N1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANSA_DATA_M2, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANSA_DATA_N2, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANSA_LINK_M1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANSA_LINK_N1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANSA_LINK_M2, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_TRANSA_LINK_N2, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_VIDEO_DIP_CTL_A, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_VIDEO_DIP_DATA_A, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_VIDEO_DIP_GCP_A, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_TRANS_DP_CTL_A, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_VIDEO_DIP_CTL_B, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_VIDEO_DIP_DATA_B, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_VIDEO_DIP_GCP_B, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_TRANS_DP_CTL_B, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_TRANSC_VIDEO_DIP_CTL, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_TRANSC_VIDEO_DIP_DATA, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_TRANSC_VIDEO_DIP_GCP, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_TRANS_DP_CTL_C, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_FDI_RXA_MISC, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_FDI_RXB_MISC, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_FDI_RXA_TUSIZE1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_FDI_RXA_TUSIZE2, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_FDI_RXB_TUSIZE1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_FDI_RXB_TUSIZE2, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_PCH_LVDS, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_DPLL_A, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_DPLL_B, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_FPA0, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_FPA1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_FPB0, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_FPB1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_DREF_CONTROL, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_RAWCLK_FREQ, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_DPLL_SEL, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ /* Linux defines as PP_ON_DEPLAY/PP_OFF_DELAY. Not in spec */
+ {0x61208, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x6120c, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_PP_ON_DELAYS, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PCH_PP_OFF_DELAYS, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_FUSE_STRAP, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_DIGITAL_PORT_HOTPLUG_CNTRL, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_DISP_ARB_CTL, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_DISP_ARB_CTL2, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_ILK_DISPLAY_CHICKEN1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_ILK_DISPLAY_CHICKEN2, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_ILK_DSPCLK_GATE_D, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_TRANSA_CHICKEN1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_TRANSB_CHICKEN1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_SOUTH_DSPCLK_GATE_D, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_TRANSA_CHICKEN2, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_TRANSB_CHICKEN2, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ /*
+ * framebuffer compression is disabled for now
+ * until it's handled at display context switch
+ * and we figure out how stolen memory should be virtualized (FBC needs use
+ * stolen memory).
+ */
+ {_REG_DPFC_CB_BASE, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {_REG_DPFC_CONTROL, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {_REG_DPFC_RECOMP_CTL, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {_REG_DPFC_CPU_FENCE_OFFSET, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {_REG_DPFC_CONTROL_SA, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {_REG_DPFC_CPU_FENCE_OFFSET_SA, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+
+ {_IPS_CTL, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+
+ {_REG_CSC_A_COEFFICIENTS, 4*6, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_CSC_A_MODE, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_PRECSC_A_HIGH_COLOR_CHANNEL_OFFSET, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_PRECSC_A_MEDIUM_COLOR_CHANNEL_OFFSET, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_PRECSC_A_LOW_COLOR_CHANNEL_OFFSET, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_REG_CSC_B_COEFFICIENTS, 4*6, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_CSC_B_MODE, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_PRECSC_B_HIGH_COLOR_CHANNEL_OFFSET, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_PRECSC_B_MEDIUM_COLOR_CHANNEL_OFFSET, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_PRECSC_B_LOW_COLOR_CHANNEL_OFFSET, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_REG_CSC_C_COEFFICIENTS, 4*6, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_CSC_C_MODE, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_PRECSC_C_HIGH_COLOR_CHANNEL_OFFSET, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_PRECSC_C_MEDIUM_COLOR_CHANNEL_OFFSET, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_PRECSC_C_LOW_COLOR_CHANNEL_OFFSET, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {0x60110, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x61110, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x70400, 0x40, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x71400, 0x40, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x72400, 0x40, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {0x70440, 0xc, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x71440, 0xc, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x72440, 0xc, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {0x7044c, 0xc, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x7144c, 0xc, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x7244c, 0xc, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_PIPE_WM_LINETIME_A, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PIPE_WM_LINETIME_B, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x45278, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_SPLL_CTL, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_WRPLL_CTL1, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_WRPLL_CTL2, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PORT_CLK_SEL_A, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PORT_CLK_SEL_B, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_PORT_CLK_SEL_DDIC, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_PORT_CLK_SEL_DDID, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_PORT_CLK_SEL_DDIE, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_TRANS_CLK_SEL_A, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_TRANS_CLK_SEL_B, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_TRANS_CLK_SEL_C, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x46408, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x46508, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x49040, 0xc, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x49140, 0xc, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x49240, 0xc, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x49080, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x49090, 0x14, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x49180, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x49190, 0x14, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x49280, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x49290, 0x14, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x4A400, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x4A480, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x4AC00, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x4AC80, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x4B400, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x4B480, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {0x6002C, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_HSW_VIDEO_DIP_CTL_A, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_HSW_VIDEO_DIP_CTL_B, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_HSW_VIDEO_DIP_CTL_C, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_REG_HSW_VIDEO_DIP_CTL_EDP, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_SFUSE_STRAP, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_SBI_ADDR, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_PIXCLK_GATE, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {0x64E60, 0x50, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x64Ec0, 0x50, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x64F20, 0x50, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x64F80, 0x50, F_DPY, 0, D_ALL, NULL, NULL},
+ {_HSW_AUD_CONFIG_A, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x650C0, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_TRANS_DDI_FUNC_CTL_A, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_TRANS_DDI_FUNC_CTL_B, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_TRANS_DDI_FUNC_CTL_C, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_TRANS_DDI_FUNC_CTL_EDP, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ {_TRANSA_MSA_MISC, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_TRANSB_MSA_MISC, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {_TRANSC_MSA_MISC, 4, F_DPY, 0, D_ALL, NULL, NULL},
+ {0x6F410, 4, F_DPY, 0, D_ALL, NULL, NULL},
+
+ /* -------others---------- */
+ {_FORCEWAKE_MT, 4, F_VIRT, 0, D_ALL, NULL, mt_force_wake_write},
+ {_FORCEWAKE_ACK_HSW, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {_ECOBUS, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RC_CONTROL, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RC_STATE, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RPNSWREQ, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RC_VIDEO_FREQ, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RP_DOWN_TIMEOUT, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RP_INTERRUPT_LIMITS, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RPSTAT1, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RP_CONTROL, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RP_UP_THRESHOLD, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RP_DOWN_THRESHOLD, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RP_CUR_UP_EI, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RP_CUR_UP, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RP_PREV_UP, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RP_CUR_DOWN_EI, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RP_CUR_DOWN, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RP_PREV_DOWN, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RP_UP_EI, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RP_DOWN_EI, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RP_IDLE_HYSTERSIS, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RC1_WAKE_RATE_LIMIT, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RC6_WAKE_RATE_LIMIT, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RC6pp_WAKE_RATE_LIMIT, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RC_EVALUATION_INTERVAL, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RC_IDLE_HYSTERSIS, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RC_SLEEP, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RC1e_THRESHOLD, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RC6_THRESHOLD, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RC6p_THRESHOLD, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_RC6pp_THRESHOLD, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_PMINTRMSK, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_GDRST, 4, F_DOM0, 0, D_ALL, NULL, gdrst_mmio_write},
+
+ {0x100000, 0x80, F_VIRT, 0, D_ALL, fence_mmio_read, fence_mmio_write},
+ {VGT_PVINFO_PAGE, VGT_PVINFO_SIZE, F_VIRT, 0, D_ALL, pvinfo_read, pvinfo_write},
+
+ /* TODO: MCHBAR, suppose read-only */
+ {MCHBAR_MIRROR_BASE_SNB, 0x40000, F_VIRT, 0, D_ALL, NULL, NULL},
+
+ {_TILECTL, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+
+ {_GEN6_UCGCTL1, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_UCGCTL2, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+
+ {_REG_SWF, 0x90, F_VIRT, 0, D_ALL, NULL, NULL},
+
+ {_GEN6_PCODE_MAILBOX, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN6_PCODE_DATA, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {0x13812c, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GEN7_ERR_INT, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0x120010, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0x9008, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {_GFX_FLSH_CNTL_GEN6, 4, F_PT, 0, D_ALL, NULL, NULL},
+
+ /* -------un-categorized regs--------- */
+ {0x3c, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {0x860, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ /* no definition on this. from Linux */
+ {_ECOSKPD, 4, F_PT, 0, D_ALL, NULL, NULL},
+ {0x121d0, 4, F_PT, 0, D_ALL, NULL, NULL},
+ {_GEN6_BLITTER_ECOSKPD, 4, F_PT, 0, D_ALL, NULL, NULL},
+ {0x41d0, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {_GAC_ECO_BITS, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {_REG_2D_CG_DIS, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {_REG_3D_CG_DIS, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {_REG_3D_CG_DIS2, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0x7118, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0x7180, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0x7408, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0x7c00, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {_GEN6_MBCTL, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0x911c, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0x9120, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+
+ {_GAB_CTL, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0x48800, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xce044, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xe6500, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xe6504, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xe6600, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xe6604, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xe6700, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xe6704, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xe6800, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xe6804, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+
+ {_REG_SUPER_QUEUE_CONFIG, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xec008, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xec00c, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xec008+0x18, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xec00c+0x18, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xec008+0x18*2, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xec00c+0x18*2, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xec008+0x18*3, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xec00c+0x18*3, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xec408, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xec40c, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xec408+0x18, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xec40c+0x18, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xec408+0x18*2, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xec40c+0x18*2, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xec408+0x18*3, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xec40c+0x18*3, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xfc810, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xfc81c, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xfc828, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xfc834, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xfcc00, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xfcc0c, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xfcc18, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xfcc24, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xfd000, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xfd00c, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xfd018, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xfd024, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+ {0xfd034, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+
+ /* MAXCNT means max idle count */
+ {_REG_RC_PWRCTX_MAXCNT, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {0x12054, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {0x22054, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+ {0x1A054, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+
+ {0x44070, 4, F_DOM0, 0, D_ALL, NULL, NULL},
+
+ {_FPGA_DBG, 4, F_VIRT, 0, D_ALL, NULL, fpga_dbg_write},
+ {_GEN6_GT_THREAD_STATUS_REG, 4, F_VIRT, 0, D_ALL, NULL, NULL},
+
+ /*command accessed registers, supplement for reg audit in cmd parser*/
+ {0x2178, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {0x217c, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {0x12178, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {0x1217c, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_BCS_SWCTRL, 4, F_RDR, 0, D_ALL, NULL, NULL},
+ {_HS_INVOCATION_COUNT, 8, F_RDR, 0, D_ALL, NULL, NULL},
+ {_DS_INVOCATION_COUNT, 8, F_RDR, 0, D_ALL, NULL, NULL},
+ {_IA_VERTICES_COUNT , 8, F_RDR, 0, D_ALL, NULL, NULL},
+ {_IA_PRIMITIVES_COUNT, 8, F_RDR, 0, D_ALL, NULL, NULL},
+ {_VS_INVOCATION_COUNT, 8, F_RDR, 0, D_ALL, NULL, NULL},
+ {_GS_INVOCATION_COUNT, 8, F_RDR, 0, D_ALL, NULL, NULL},
+ {_GS_PRIMITIVES_COUNT, 8, F_RDR, 0, D_ALL, NULL, NULL},
+ {_CL_INVOCATION_COUNT, 8, F_RDR, 0, D_ALL, NULL, NULL},
+ {_CL_PRIMITIVES_COUNT, 8, F_RDR, 0, D_ALL, NULL, NULL},
+ {_PS_INVOCATION_COUNT, 8, F_RDR, 0, D_ALL, NULL, NULL},
+ {_PS_DEPTH_COUNT, 8, F_RDR, 0, D_ALL, NULL, NULL},
+
+ /* BDW */
+ {0xe100, 4, F_RDR, 0, D_ALL, NULL, NULL},
};
struct gvt_reg_info gvt_broadwell_reg_info[] = {
-{0, 0, 0, 0, 0, NULL, NULL},
+ /* Interrupt registers - GT */
+ {_RING_IMR(GEN8_BSD2_RING_BASE), 4, F_RDR, 0, D_BDW_PLUS, NULL, gvt_reg_imr_handler},
+
+ /* Interrupt registers - BDW */
+ {_REG_GT_IMR(0), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_imr_handler},
+ {_REG_GT_IER(0), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_ier_handler},
+ {_REG_GT_IIR(0), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_iir_handler},
+ {_REG_GT_ISR(0), 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_GT_IMR(1), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_imr_handler},
+ {_REG_GT_IER(1), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_ier_handler},
+ {_REG_GT_IIR(1), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_iir_handler},
+ {_REG_GT_ISR(1), 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_GT_IMR(2), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_imr_handler},
+ {_REG_GT_IER(2), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_ier_handler},
+ {_REG_GT_IIR(2), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_iir_handler},
+ {_REG_GT_ISR(2), 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_GT_IMR(3), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_imr_handler},
+ {_REG_GT_IER(3), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_ier_handler},
+ {_REG_GT_IIR(3), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_iir_handler},
+ {_REG_GT_ISR(3), 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_DE_PIPE_IMR(PIPE_A), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_imr_handler},
+ {_REG_DE_PIPE_IER(PIPE_A), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_ier_handler},
+ {_REG_DE_PIPE_IIR(PIPE_A), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_iir_handler},
+ {_REG_DE_PIPE_ISR(PIPE_A), 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_DE_PIPE_IMR(PIPE_B), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_imr_handler},
+ {_REG_DE_PIPE_IER(PIPE_B), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_ier_handler},
+ {_REG_DE_PIPE_IIR(PIPE_B), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_iir_handler},
+ {_REG_DE_PIPE_ISR(PIPE_B), 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_DE_PIPE_IMR(PIPE_C), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_imr_handler},
+ {_REG_DE_PIPE_IER(PIPE_C), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_ier_handler},
+ {_REG_DE_PIPE_IIR(PIPE_C), 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_iir_handler},
+ {_REG_DE_PIPE_ISR(PIPE_C), 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_GEN8_DE_PORT_IMR, 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_imr_handler},
+ {_GEN8_DE_PORT_IER, 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_ier_handler},
+ {_GEN8_DE_PORT_IIR, 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_iir_handler},
+ {_GEN8_DE_PORT_ISR, 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_GEN8_DE_MISC_IMR, 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_imr_handler},
+ {_GEN8_DE_MISC_IER, 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_ier_handler},
+ {_GEN8_DE_MISC_IIR, 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_iir_handler},
+ {_GEN8_DE_MISC_ISR, 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_GEN8_PCU_IMR, 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_imr_handler},
+ {_GEN8_PCU_IER, 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_ier_handler},
+ {_GEN8_PCU_IIR, 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_iir_handler},
+ {_GEN8_PCU_ISR, 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_GEN8_MASTER_IRQ, 4, F_VIRT, 0, D_BDW_PLUS, NULL, gvt_reg_master_irq_handler},
+
+ /* -------render regs---------- */
+ {_RING_HWSTAM(GEN8_BSD2_RING_BASE), 4, F_RDR, 0, D_BDW_PLUS, NULL, NULL},
+
+ /* maybe an error in Linux driver. meant for VCS_HWS_PGA */
+ {_REG_VCS2_UHPTR, 4, F_RDR_HWSTS, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_RING_TAIL(GEN8_BSD2_RING_BASE), 4, F_RDR, 0, D_BDW_PLUS, NULL, NULL},
+ {_RING_HEAD(GEN8_BSD2_RING_BASE), 4, F_RDR, 0, D_BDW_PLUS, NULL, NULL},
+ {_RING_START(GEN8_BSD2_RING_BASE), 4, F_RDR_ADRFIX, 0xFFFFF000, D_BDW_PLUS,
+ NULL, NULL},
+ {_RING_CTL(GEN8_BSD2_RING_BASE), 4, F_RDR, 0, D_BDW_PLUS, NULL, NULL},
+ {_RING_ACTHD(GEN8_BSD2_RING_BASE), 4, F_RDR, 0, D_BDW_PLUS, NULL, NULL},
+ {GVT_RING_MODE(GEN8_BSD2_RING_BASE), 4, F_RDR_MODE, 0, D_BDW_PLUS, NULL, ring_mode_write},
+ {_RING_MI_MODE(GEN8_BSD2_RING_BASE), 4, F_RDR_MODE, 0, D_BDW_PLUS, NULL, NULL},
+ {_RING_INSTPM(GEN8_BSD2_RING_BASE), 4, F_RDR_MODE, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_RCS_ACTHD_UDW, 4, F_RDR, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_BCS_ACTHD_UDW, 4, F_RDR, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VCS_ACTHD_UDW, 4, F_RDR, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VCS2_ACTHD_UDW, 4, F_RDR, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VECS_ACTHD_UDW, 4, F_RDR, 0, D_BDW_PLUS, NULL, NULL},
+
+ /* TODO: need a handler */
+ {0x1c050, 4, F_PT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_VCS2_TIMESTAMP, 8, F_PT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_RCS_EXECLIST_SUBMITPORT, 4, F_VIRT, 0, D_BDW_PLUS,
+ mmio_not_allow_read, NULL},
+ {_REG_VCS_EXECLIST_SUBMITPORT, 4, F_VIRT, 0, D_BDW_PLUS,
+ mmio_not_allow_read, NULL},
+ {_REG_VECS_EXECLIST_SUBMITPORT, 4, F_VIRT, 0, D_BDW_PLUS,
+ mmio_not_allow_read, NULL},
+ {_REG_VCS2_EXECLIST_SUBMITPORT, 4, F_VIRT, 0, D_BDW_PLUS,
+ mmio_not_allow_read, NULL},
+ {_REG_BCS_EXECLIST_SUBMITPORT, 4, F_VIRT, 0, D_BDW_PLUS,
+ mmio_not_allow_read, NULL},
+
+ {_REG_RCS_EXECLIST_STATUS, 8, F_RDR, 0, D_BDW_PLUS, NULL,
+ mmio_not_allow_write},
+ {_REG_VCS_EXECLIST_STATUS, 8, F_RDR, 0, D_BDW_PLUS, NULL,
+ mmio_not_allow_write},
+ {_REG_VECS_EXECLIST_STATUS, 8, F_RDR, 0, D_BDW_PLUS, NULL,
+ mmio_not_allow_write},
+ {_REG_VCS2_EXECLIST_STATUS, 8, F_RDR, 0, D_BDW_PLUS, NULL,
+ mmio_not_allow_write},
+ {_REG_BCS_EXECLIST_STATUS, 8, F_RDR, 0, D_BDW_PLUS, NULL,
+ mmio_not_allow_write},
+
+ {_REG_RCS_CTX_SR_CTL, 4, F_RDR, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VCS_CTX_SR_CTL, 4, F_RDR, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VECS_CTX_SR_CTL, 4, F_RDR, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VCS2_CTX_SR_CTL, 4, F_RDR, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_BCS_CTX_SR_CTL, 4, F_RDR, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_RCS_CTX_STATUS_BUF, 48, F_VIRT, 0, D_BDW_PLUS, NULL,
+ mmio_not_allow_write},
+ {_REG_VCS_CTX_STATUS_BUF, 48, F_VIRT, 0, D_BDW_PLUS, NULL,
+ mmio_not_allow_write},
+ {_REG_VECS_CTX_STATUS_BUF, 48, F_VIRT, 0, D_BDW_PLUS, NULL,
+ mmio_not_allow_write},
+ {_REG_VCS2_CTX_STATUS_BUF, 48, F_VIRT, 0, D_BDW_PLUS, NULL,
+ mmio_not_allow_write},
+ {_REG_BCS_CTX_STATUS_BUF, 48, F_VIRT, 0, D_BDW_PLUS, NULL,
+ mmio_not_allow_write},
+
+ {_REG_RCS_CTX_STATUS_PTR, 4, F_VIRT | GVT_REG_MODE_CTL, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VCS_CTX_STATUS_PTR, 4, F_VIRT | GVT_REG_MODE_CTL, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VECS_CTX_STATUS_PTR, 4, F_VIRT | GVT_REG_MODE_CTL, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VCS2_CTX_STATUS_PTR, 4, F_VIRT | GVT_REG_MODE_CTL, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_BCS_CTX_STATUS_PTR, 4, F_VIRT | GVT_REG_MODE_CTL, 0, D_BDW_PLUS, NULL, NULL},
+ /* -------display regs---------- */
+
+ {_PIPE_MISC_A, 4, F_DPY, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_PIPE_MISC_B, 4, F_DPY, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_PIPE_MISC_C, 4, F_DPY, 0, D_BDW_PLUS, NULL, NULL},
+
+ /* -------others---------- */
+
+ /* -------un-categorized regs--------- */
+ /* no definition on this. from Linux */
+ {0x1c1d0, 4, F_PT, 0, D_BDW_PLUS, NULL, NULL},
+ {_GEN6_MBCUNIT_SNPCR, 4, F_PT, 0, D_BDW_PLUS, NULL, NULL},
+ {_GEN7_MISCCPCTL, 4, F_PT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {0x1C054, 4, F_DOM0, 0, D_BDW_PLUS, NULL, NULL},
+ /* BDW */
+ {_GEN8_PRIVATE_PAT_LO, 4, F_PT, 0, D_BDW_PLUS, NULL, NULL},
+ {_GEN8_PRIVATE_PAT_HI, 4, F_PT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_GAMTARBMODE, 4, F_DOM0, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_RCS_PDP_UDW(0) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_RCS_PDP_LDW(0) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_RCS_PDP_UDW(1) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_RCS_PDP_LDW(1) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_RCS_PDP_UDW(2) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_RCS_PDP_LDW(2) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_RCS_PDP_UDW(3) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_RCS_PDP_LDW(3) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_VCS_PDP_UDW(0) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VCS_PDP_LDW(0) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_VCS_PDP_UDW(1) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VCS_PDP_LDW(1) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_VCS_PDP_UDW(2) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VCS_PDP_LDW(2) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_VCS_PDP_UDW(3) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VCS_PDP_LDW(3) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_VECS_PDP_UDW(0) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VECS_PDP_LDW(0) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_VECS_PDP_UDW(1) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VECS_PDP_LDW(1) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_VECS_PDP_UDW(2) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VECS_PDP_LDW(2) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_VECS_PDP_UDW(3) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VECS_PDP_LDW(3) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_VCS2_PDP_UDW(0) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VCS2_PDP_LDW(0) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_VCS2_PDP_UDW(1) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VCS2_PDP_LDW(1) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_VCS2_PDP_UDW(2) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VCS2_PDP_LDW(2) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_VCS2_PDP_UDW(3) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_VCS2_PDP_LDW(3) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_BCS_PDP_UDW(0) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_BCS_PDP_LDW(0) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_BCS_PDP_UDW(1) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_BCS_PDP_LDW(1) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_BCS_PDP_UDW(2) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_BCS_PDP_LDW(2) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {_REG_BCS_PDP_UDW(3) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {_REG_BCS_PDP_LDW(3) , 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+
+ {0x2080, 4, F_RDR_ADRFIX, 0xFFFFF000, D_BDW_PLUS, NULL, NULL},
+ {0x12080, 4, F_RDR_ADRFIX, 0xFFFFF000, D_BDW_PLUS, NULL, NULL},
+ {0x1c080, 4, F_RDR_ADRFIX, 0xFFFFF000, D_BDW_PLUS, NULL, NULL},
+ {0x1a080, 4, F_RDR_ADRFIX, 0xFFFFF000, D_BDW_PLUS, NULL, NULL},
+ {0x22080, 4, F_RDR_ADRFIX, 0xFFFFF000, D_BDW_PLUS, NULL, NULL},
+
+ {0x7300, 4, F_RDR, 0, D_BDW_PLUS, NULL, NULL},
+
+ {0x420b0, 4, F_DPY, 0, D_BDW, NULL, NULL},
+ {0x420b4, 4, F_DPY, 0, D_BDW, NULL, NULL},
+ {0x420b8, 4, F_DPY, 0, D_BDW, NULL, NULL},
+
+ {0x45260, 4, F_DPY, 0, D_BDW, NULL, NULL},
+ {0x6f800, 4, F_DPY, 0, D_BDW, NULL, NULL},
+
+ {0x66c00, 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
+ {0x66c04, 4, F_VIRT, 0, D_BDW, NULL, NULL},
+
+ {0x4024, 4, F_DOM0, 0, D_BDW, NULL, NULL},
+
+ {0x9134, 4, F_VIRT, 0, D_BDW, NULL, NULL},
+ {0x9138, 4, F_VIRT, 0, D_BDW, NULL, NULL},
+ {0x913c, 4, F_VIRT, 0, D_BDW, NULL, NULL},
+
+ /* WA */
+ {0xfdc, 4, F_DOM0, 0, D_BDW, NULL, NULL},
+ {0xe4f0, 4, F_RDR, 0, D_BDW, NULL, NULL},
+ {0xe4f4, 4, F_RDR, 0, D_BDW, NULL, NULL},
+ {0x9430, 4, F_RDR, 0, D_BDW, NULL, NULL},
+
+ /* L3 */
+ {0xb1f0, 4, F_RDR, 0, D_BDW, NULL, NULL},
+ {0xb1c0, 4, F_RDR, 0, D_BDW, NULL, NULL},
+ {0xb118, 4, F_RDR, 0, D_BDW, NULL, NULL},
+ {0xb100, 4, F_RDR, 0, D_BDW, NULL, NULL},
+ {0xb10c, 4, F_RDR, 0, D_BDW, NULL, NULL},
+ {0xb110, 4, F_PT, 0, D_BDW, NULL, NULL},
+
+ /* NON-PRIV */
+ {0x24d0, 4, F_RDR, 0, D_BDW, NULL, NULL},
+ {0x24d4, 4, F_RDR, 0, D_BDW, NULL, NULL},
+ {0x24d8, 4, F_RDR, 0, D_BDW, NULL, NULL},
+ {0x24dc, 4, F_RDR, 0, D_BDW, NULL, NULL},
+
+ {0x83a4, 4, F_RDR, 0, D_BDW, NULL, NULL},
+ {0x4dd4, 4, F_PT, 0, D_BDW, NULL, NULL},
+
+ /* UCG */
+ {0x8430, 4, F_PT, 0, D_BDW, NULL, NULL},
+
+ {0x110000, 4, F_VIRT, 0, D_BDW_PLUS, NULL, NULL},
};
int gvt_get_reg_num(int type)
{
- switch(type){
+ switch (type) {
case D_ALL:
return ARRAY_SIZE(gvt_general_reg_info);
case D_BDW:
@@ -42,6 +1131,5 @@ int gvt_get_reg_num(int type)
default:
return 0;
}
-
return 0;
}
diff --git a/drivers/gpu/drm/i915/gvt/instance.c b/drivers/gpu/drm/i915/gvt/instance.c
index 91f52c6..0bf62e4 100644
--- a/drivers/gpu/drm/i915/gvt/instance.c
+++ b/drivers/gpu/drm/i915/gvt/instance.c
@@ -228,6 +228,8 @@ struct vgt_device *gvt_create_instance(struct pgt_device *pdev,
vgt->id = id;
vgt->pdev = pdev;
+ vgt->warn_untrack = true;
+
if (!create_virtual_device_state(vgt, info))
goto err;
diff --git a/drivers/gpu/drm/i915/gvt/interrupt.h b/drivers/gpu/drm/i915/gvt/interrupt.h
index cee85b6..3142ed6 100644
--- a/drivers/gpu/drm/i915/gvt/interrupt.h
+++ b/drivers/gpu/drm/i915/gvt/interrupt.h
@@ -229,4 +229,18 @@ struct gvt_irq_state {
bool gvt_irq_init(struct pgt_device *pdev);
void gvt_irq_exit(struct pgt_device *pdev);
+bool gvt_reg_imr_handler(struct vgt_device *vgt,
+ unsigned int reg, void *p_data, unsigned int bytes);
+bool gvt_reg_ier_handler(struct vgt_device *vgt,
+ unsigned int reg, void *p_data, unsigned int bytes);
+bool gvt_reg_iir_handler(struct vgt_device *vgt, unsigned int reg,
+ void *p_data, unsigned int bytes);
+bool gvt_reg_isr_write(struct vgt_device *vgt, unsigned int reg,
+ void *p_data, unsigned int bytes);
+bool gvt_reg_master_irq_handler(struct vgt_device *vgt,
+ unsigned int reg, void *p_data, unsigned int bytes);
+void gvt_trigger_virtual_event(struct vgt_device *vgt,
+ enum gvt_event_type event);
+void gvt_inject_flip_done(struct vgt_device *vgt, int pipe);
+
#endif /* _GVT_INTERRUPT_H_ */
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index 3297d82..e83ad1e 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -23,7 +23,7 @@
#include "gvt.h"
-static inline unsigned int get_device_type(struct pgt_device *pdev)
+unsigned int gvt_get_device_type(struct pgt_device *pdev)
{
if (IS_BROADWELL(pdev->dev_priv))
return D_BDW;
@@ -32,7 +32,7 @@ static inline unsigned int get_device_type(struct pgt_device *pdev)
static inline bool match_device(struct pgt_device *pdev, struct gvt_reg_info *info)
{
- return info->device & get_device_type(pdev);
+ return info->device & gvt_get_device_type(pdev);
}
static void save_initial_mmio_state(struct pgt_device *pdev,
@@ -514,3 +514,32 @@ err:
mutex_unlock(&pdev->lock);
return false;
}
+
+static unsigned long ring_mmio_base[] = {
+ [RCS] = RENDER_RING_BASE,
+ [BCS] = BLT_RING_BASE,
+ [VCS] = GEN6_BSD_RING_BASE,
+ [VECS] = VEBOX_RING_BASE,
+ [VCS2] = GEN8_BSD2_RING_BASE,
+};
+
+int gvt_render_mmio_to_ring_id(unsigned int reg)
+{
+ int i;
+
+ reg &= ~0xfff;
+
+ for (i = 0; i < ARRAY_SIZE(ring_mmio_base); i++) {
+ if (ring_mmio_base[i] == reg)
+ return i;
+ }
+
+ ASSERT(0);
+ return -1;
+}
+
+int gvt_ring_id_to_render_mmio_base(int ring_id)
+{
+ ASSERT(ring_id >= 0 && ring_id < (ARRAY_SIZE(ring_mmio_base)));
+ return ring_mmio_base[ring_id];
+}
diff --git a/drivers/gpu/drm/i915/gvt/mmio.h b/drivers/gpu/drm/i915/gvt/mmio.h
index 4301655..71ae47b 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.h
+++ b/drivers/gpu/drm/i915/gvt/mmio.h
@@ -48,6 +48,18 @@
#define GVT_AUX_TABLE_NUM 256
+#define F_VIRT GVT_REG_VIRT
+
+#define F_DOM0 F_VIRT
+#define F_RDR F_VIRT
+#define F_RDR_ADRFIX F_VIRT
+#define F_RDR_HWSTS F_VIRT
+#define F_RDR_MODE F_VIRT
+#define F_DPY F_VIRT
+#define F_DPY_ADRFIX F_VIRT
+#define F_DPY_HWSTS_ADRFIX F_VIRT
+#define F_PT F_VIRT
+
/* suppose a reg won't set both bits */
typedef union {
struct {
@@ -81,11 +93,13 @@ struct gvt_reg_info {
gvt_mmio_handler_t write;
};
+struct pgt_device;
+
extern struct gvt_reg_info gvt_general_reg_info[];
extern struct gvt_reg_info gvt_broadwell_reg_info[];
extern int gvt_get_reg_num(int type);
+extern unsigned int gvt_get_device_type(struct pgt_device *pdev);
bool gvt_emulate_mmio_read(struct vgt_device *vgt, uint64_t pa, void *p_data,int bytes);
bool gvt_emulate_mmio_write(struct vgt_device *vgt, uint64_t pa, void *p_data,int bytes);
-
#endif
diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
index c66a2dc..1758092 100644
--- a/drivers/gpu/drm/i915/gvt/reg.h
+++ b/drivers/gpu/drm/i915/gvt/reg.h
@@ -68,6 +68,107 @@
#define _REGBIT_BDW_GMCH_GMS_SHIFT 8
#define _REGBIT_BDW_GMCH_GMS_MASK 0xff
+#define _GVT_MMIO_THROUGH_OFFSET(index, a, b) ((a) + (index)*((b)-(a)))
+#define _GVT_MMIO_GET_INDEX(reg, a, b) (((reg)-(a))/((b)-(a)))
+
+#define _GVT_GET_PIPE(reg, a, b) _GVT_MMIO_GET_INDEX(reg, a, b)
+#define _GVT_GET_PORT(reg, a, b) _GVT_MMIO_GET_INDEX(reg, a, b)
+
+#define _REG_GAC_MODE 0x120A0
+#define _REG_GAB_MODE 0x220A0
+
+#define _REG_RCS_BB_ADDR 0x2140
+#define _REG_VCS_BB_ADDR 0x12140
+#define _REG_BCS_BB_ADDR 0x22140
+#define _REG_VECS_BB_ADDR 0x1A140
+#define _REG_VCS2_BB_ADDR 0x1c140
+
+#define _REG_VECS_CTX_WA_BB_ADDR 0x1A144
+
+#define _REG_RCS_EXCC 0x2028
+#define _REG_VCS_EXCC 0x12028
+#define _REG_BCS_EXCC 0x22028
+#define _REG_VECS_EXCC 0x1A028
+#define _REG_VCS2_EXCC 0x1c028
+
+#define _REG_RCS_UHPTR 0x2134
+#define _REG_VCS_UHPTR 0x12134
+#define _REG_BCS_UHPTR 0x22134
+#define _REG_VECS_UHPTR 0x1A134
+#define _REG_VCS2_UHPTR 0x1c134
+
+#define _REG_RCS_ACTHD_UDW 0x205c
+#define _REG_VCS_ACTHD_UDW 0x1205c
+#define _REG_BCS_ACTHD_UDW 0x2205c
+#define _REG_VECS_ACTHD_UDW 0x1A05c
+#define _REG_VCS2_ACTHD_UDW 0x1c05c
+
+#define _REG_RCS_BB_PREEMPT_ADDR 0x2148
+#define _REG_RCS_BB_ADDR_DIFF 0x2154
+
+#define _REG_RCS_TIMESTAMP 0x2358
+#define _REG_VCS_TIMESTAMP 0x12358
+#define _REG_VCS2_TIMESTAMP 0x1c358
+#define _REG_BCS_TIMESTAMP 0x22358
+
+#define GVT_RING_MODE(base) (base + 0x29c)
+
+#define RB_HEAD_OFF_MASK ((1U << 21) - (1U << 2))
+#define RB_TAIL_OFF_MASK ((1U << 21) - (1U << 3)) /* bit 3 to 20 */
+#define RB_TAIL_SIZE_MASK ((1U << 21) - (1U << 12)) /* bit 12 to 20 */
+#define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + GTT_PAGE_SIZE)
+
+#define _EL_BASE_RCS 0x02000
+#define _EL_BASE_VCS 0x12000
+#define _EL_BASE_VECS 0x1A000
+#define _EL_BASE_VCS2 0x1C000
+#define _EL_BASE_BCS 0x22000
+
+#define _EL_OFFSET_SUBMITPORT 0x230
+#define _EL_OFFSET_STATUS 0x234
+#define _EL_OFFSET_SR_CTL 0x244
+#define _EL_OFFSET_STATUS_BUF 0x370
+#define _EL_OFFSET_STATUS_PTR 0x3A0
+
+#define _REG_RCS_EXECLIST_SUBMITPORT 0x02230
+#define _REG_VCS_EXECLIST_SUBMITPORT 0x12230
+#define _REG_VECS_EXECLIST_SUBMITPORT 0x1A230
+#define _REG_VCS2_EXECLIST_SUBMITPORT 0x1C230
+#define _REG_BCS_EXECLIST_SUBMITPORT 0x22230
+
+#define _EXECLIST_LRCA_MASK 0xfffff000
+
+#define _REG_RCS_EXECLIST_STATUS 0x02234
+#define _REG_VCS_EXECLIST_STATUS 0x12234
+#define _REG_VECS_EXECLIST_STATUS 0x1A234
+#define _REG_VCS2_EXECLIST_STATUS 0x1C234
+#define _REG_BCS_EXECLIST_STATUS 0x22234
+
+#define _REG_RCS_CTX_SR_CTL 0x02244
+#define _REG_VCS_CTX_SR_CTL 0x12244
+#define _REG_VECS_CTX_SR_CTL 0x1A244
+#define _REG_VCS2_CTX_SR_CTL 0x1C244
+#define _REG_BCS_CTX_SR_CTL 0x22244
+
+#define _REG_RCS_CTX_STATUS_BUF 0x02370
+#define _REG_VCS_CTX_STATUS_BUF 0x12370
+#define _REG_VECS_CTX_STATUS_BUF 0x1A370
+#define _REG_VCS2_CTX_STATUS_BUF 0x1C370
+#define _REG_BCS_CTX_STATUS_BUF 0x22370
+
+#define _REG_RCS_CTX_STATUS_PTR 0x023A0
+#define _REG_VCS_CTX_STATUS_PTR 0x123A0
+#define _REG_VECS_CTX_STATUS_PTR 0x1A3A0
+#define _REG_VCS2_CTX_STATUS_PTR 0x1C3A0
+#define _REG_BCS_CTX_STATUS_PTR 0x223A0
+
+#define _REG_CURASURFLIVE 0x700AC
+
+#define _REG_CURAPALET_0 0x70090
+#define _REG_CURAPALET_1 0x70094
+#define _REG_CURAPALET_2 0x70098
+#define _REG_CURAPALET_3 0x7009C
+
#define _PRI_PLANE_FMT_SHIFT 26
#define _PRI_PLANE_TILE_SHIFT 10
@@ -475,6 +576,80 @@ union _TRANS_CONFIG
#define _GEN6_GT_THREAD_STATUS_REG 0x13805c
#define _GEN6_GT_CORE_STATUS 0x138060
+#define _FORCEWAKE_MT 0xa188
+#define _FORCEWAKE_ACK_HSW 0x130044
+#define _SBI_ADDR 0xC6000
+#define _SBI_DATA 0xC6004
+#define _SBI_CTL_STAT 0xC6008
+
+#define _RING_IMR(base) ((base) + 0xa8)
+#define _SPLL_CTL 0x46020
+#define _SFUSE_STRAP 0xc2014
+#define _PIXCLK_GATE 0xC6020
+#define _ECOBUS 0xa180
+#define _GEN6_RC_CONTROL 0xA090
+#define _GEN6_RC_STATE 0xA094
+#define _GEN6_RPNSWREQ (0xA008)
+#define _GEN6_RC_VIDEO_FREQ (0xA00C)
+#define _GEN6_RP_DOWN_TIMEOUT (0xA010)
+#define _GEN6_RP_INTERRUPT_LIMITS (0xA014)
+#define _GEN6_RPSTAT1 (0xA01C)
+#define _GEN6_RP_CONTROL (0xA024)
+#define _GEN6_RP_UP_THRESHOLD (0xA02C)
+#define _GEN6_RP_DOWN_THRESHOLD (0xA030)
+#define _GEN6_RP_CUR_UP_EI (0xA050)
+#define _GEN6_RP_CUR_UP (0xA054)
+#define _GEN6_RP_PREV_UP (0xA058)
+#define _GEN6_RP_CUR_DOWN_EI (0xA05C)
+#define _GEN6_RP_CUR_DOWN (0xA060)
+#define _GEN6_RP_PREV_DOWN (0xA064)
+#define _GEN6_RP_UP_EI (0xA068)
+#define _GEN6_RP_DOWN_EI (0xA06C)
+#define _GEN6_RP_IDLE_HYSTERSIS (0xA070)
+#define _GEN6_RC1_WAKE_RATE_LIMIT (0xA098)
+#define _GEN6_RC6_WAKE_RATE_LIMIT (0xA09C)
+#define _GEN6_RC6pp_WAKE_RATE_LIMIT (0xA0A0)
+#define _GEN6_RC_EVALUATION_INTERVAL (0xA0A8)
+#define _GEN6_RC_IDLE_HYSTERSIS (0xA0AC)
+#define _GEN6_RC_SLEEP (0xA0B0)
+#define _GEN6_RC1e_THRESHOLD (0xA0B4)
+#define _GEN6_RC6_THRESHOLD (0xA0B8)
+#define _GEN6_RC6p_THRESHOLD (0xA0BC)
+#define _GEN6_RC6pp_THRESHOLD (0xA0C0)
+#define _GEN6_PMINTRMSK (0xA168)
+#define _HSW_PWR_WELL_BIOS (0x45400)
+#define _HSW_PWR_WELL_DRIVER (0x45404)
+#define _HSW_PWR_WELL_KVMR (0x45408)
+#define _HSW_PWR_WELL_DEBUG (0x4540C)
+#define _HSW_PWR_WELL_CTL5 (0x45410)
+#define _HSW_PWR_WELL_CTL6 (0x45414)
+#define _CPU_VGACNTRL (0x41000)
+#define _TILECTL (0x101000)
+#define _GEN6_UCGCTL1 (0x9400)
+#define _GEN6_UCGCTL2 (0x9404)
+#define _GEN6_PCODE_MAILBOX (0x138124)
+#define _GEN6_PCODE_DATA (0x138128)
+#define _GEN7_ERR_INT (0x44040)
+#define _GFX_FLSH_CNTL_GEN6 (0x101008)
+#define _ECOSKPD (0x21d0)
+#define _GEN6_BLITTER_ECOSKPD (0x221d0)
+#define _GAC_ECO_BITS (0x14090)
+#define _GEN6_MBCTL (0x0907c)
+#define _GAB_CTL (0x24000)
+#define _FPGA_DBG (0x42300)
+#define _BCS_SWCTRL (0x22200)
+#define _HS_INVOCATION_COUNT (0x2300)
+#define _DS_INVOCATION_COUNT (0x2308)
+#define _IA_VERTICES_COUNT (0x2310)
+#define _IA_PRIMITIVES_COUNT (0x2318)
+#define _VS_INVOCATION_COUNT (0x2320)
+#define _GS_INVOCATION_COUNT (0x2328)
+#define _GS_PRIMITIVES_COUNT (0x2330)
+#define _CL_INVOCATION_COUNT (0x2338)
+#define _CL_PRIMITIVES_COUNT (0x2340)
+#define _PS_INVOCATION_COUNT (0x2348)
+#define _PS_DEPTH_COUNT (0x2350)
+
#define _GEN8_DE_PORT_IMR (0x44444)
#define _GEN8_DE_PORT_IER (0x4444c)
#define _GEN8_DE_PORT_IIR (0x44448)
@@ -491,11 +666,75 @@ union _TRANS_CONFIG
#define _GEN8_PCU_ISR (0x444e0)
#define _GEN8_MASTER_IRQ (0x44200)
+#define _RING_HWSTAM(base) ((base)+0x98)
+#define _RING_TAIL(base) ((base)+0x30)
+#define _RING_HEAD(base) ((base)+0x34)
+#define _RING_START(base) ((base)+0x38)
+#define _RING_CTL(base) ((base)+0x3c)
+#define _RING_ACTHD(base) ((base)+0x74)
+#define _RING_MI_MODE(base) ((base)+0x9c)
+#define _RING_INSTPM(base) ((base)+0xc0)
+
+#define _GEN6_MBCUNIT_SNPCR (0x900c)
+#define _GEN7_MISCCPCTL (0x9424)
+#define _GEN8_PRIVATE_PAT_LO (0x40e0)
+#define _GEN8_PRIVATE_PAT_HI (0x40e0 + 4)
+#define _GAMTARBMODE (0x04a08)
+
#define _SDEIMR (0xc4004)
#define _SDEIER (0xc400c)
#define _SDEIIR (0xc4008)
#define _SDEISR (0xc4000)
+#define _RENDER_HWS_PGA_GEN7 (0x04080)
+#define _BSD_HWS_PGA_GEN7 (0x04180)
+#define _BLT_HWS_PGA_GEN7 (0x04280)
+#define _VEBOX_HWS_PGA_GEN7 (0x04380)
+#define _RING_MI_MODE(base) ((base)+0x9c)
+#define _GEN7_GT_MODE (0x7008)
+#define _CACHE_MODE_0_GEN7 (0x7000) /* IVB+ */
+#define _CACHE_MODE_1 (0x7004) /* IVB+ */
+#define _GAM_ECOCHK (0x4090)
+#define _GEN7_COMMON_SLICE_CHICKEN1 (0x7010)
+#define _COMMON_SLICE_CHICKEN2 (0x7014)
+#define _VGA0 (0x6000)
+#define _VGA1 (0x6004)
+#define _VGA_PD (0x6010)
+#define _DERRMR (0x44050)
+#define _WM0_PIPEA_ILK (0x45100)
+#define _WM0_PIPEB_ILK (0x45104)
+#define _WM0_PIPEC_IVB (0x45200)
+#define _WM1_LP_ILK (0x45108)
+#define _WM2_LP_ILK (0x4510c)
+#define _WM3_LP_ILK (0x45110)
+#define _WM1S_LP_ILK (0x45120)
+#define _WM2S_LP_IVB (0x45124)
+#define _WM3S_LP_IVB (0x45128)
+#define _BLC_PWM_CPU_CTL2 (0x48250)
+#define _BLC_PWM_CPU_CTL (0x48254)
+#define _BLC_PWM_PCH_CTL1 (0xc8250)
+#define _BLC_PWM_PCH_CTL2 (0xc8254)
+#define _PCH_GPIOA (0xc5010)
+#define _PCH_ADPA (0xe1100)
+#define __3D_CHICKEN3 (0x2090)
+#define _PCH_LVDS (0xe1180)
+#define _PCH_DREF_CONTROL (0xC6200)
+#define _PCH_RAWCLK_FREQ (0xc6204)
+#define _PCH_DPLL_SEL (0xc7000)
+#define _PCH_PORT_HOTPLUG (0xc4030) /* SHOTPLUG_CTL */
+#define _LCPLL_CTL (0x130040)
+#define _FUSE_STRAP (0x42014)
+#define _DIGITAL_PORT_HOTPLUG_CNTRL (0x44030)
+#define _DISP_ARB_CTL (0x45000)
+#define _DISP_ARB_CTL2 (0x45004)
+#define _ILK_DISPLAY_CHICKEN1 (0x42000)
+#define _ILK_DISPLAY_CHICKEN2 (0x42004)
+#define _ILK_DSPCLK_GATE_D (0x42020)
+#define _SOUTH_CHICKEN1 (0xc2000)
+#define _SOUTH_CHICKEN2 (0xc2004)
+#define _SOUTH_DSPCLK_GATE_D (0xc2020)
+#define _IPS_CTL (0x43408)
+
#define _GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
#define _GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
#define _GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
@@ -506,7 +745,142 @@ union _TRANS_CONFIG
#define _GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
#define _GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
+/* digital port hotplug */
+/* GMBUS1 bits definitions */
+
+#define GMBUS1_TOTAL_BYTES_SHIFT 16
+#define GMBUS1_TOTAL_BYTES_MASK 0x1ff
+#define gmbus1_total_byte_count(v) (((v) >> GMBUS1_TOTAL_BYTES_SHIFT) & GMBUS1_TOTAL_BYTES_MASK)
+#define gmbus1_slave_addr(v) (((v) & 0xff) >> 1)
+#define gmbus1_slave_index(v) (((v) >> 8) & 0xff)
+#define gmbus1_bus_cycle(v) (((v) >> 25) & 0x7)
+
+/* GMBUS0 bits definitions */
+#define _GMBUS_PIN_SEL_MASK (0x7)
+
+#define _REG_RC_PWRCTX_MAXCNT 0x2054
+#define _REG_VFSKPD 0x2470
+#define _REG_2D_CG_DIS 0x6200
+#define _REG_3D_CG_DIS 0x6204
+#define _REG_3D_CG_DIS2 0x6208
+#define _REG_SUPER_QUEUE_CONFIG 0x902c
+
+/* interrupt related definitions */
+#define _REGSHIFT_MASTER_INTERRUPT 31
+#define _REGSHIFT_PCH 21
+#define _REGBIT_PCH (1 << 21)
+/* GEN7 */
+#define _REGSHIFT_PCH_GEN7 28
+#define _REGBIT_PCH_GEN7 (1 << 28)
+
+#define _REGBIT_DP_A_PULSE_DURATION (3 << 2)
+
+#define _REGBIT_CRT_HOTPLUG (1 << 19)
+#define _REGBIT_DP_B_HOTPLUG (1 << 21)
+#define _REGBIT_DP_C_HOTPLUG (1 << 22)
+#define _REGBIT_DP_D_HOTPLUG (1 << 23)
+
+#define _REGBIT_DP_B_STATUS (3 << 0)
+#define _REGBIT_DP_B_PULSE_DURATION (3 << 2)
+#define _REGBIT_DP_B_ENABLE (1 << 4)
+#define _REGBIT_DP_C_STATUS (3 << 8)
+#define _REGBIT_DP_C_PULSE_DURATION (3 << 10)
+#define _REGBIT_DP_C_ENABLE (1 << 12)
+#define _REGBIT_DP_D_STATUS (3 << 16)
+#define _REGBIT_DP_D_PULSE_DURATION (3 << 18)
+#define _REGBIT_DP_D_ENABLE (1 << 20)
+
+#define _REG_RCS_WATCHDOG_CTL 0x2178
+#define _REG_RCS_WATCHDOG_THRSH 0x217C
+#define _REG_RCS_WATCHDOG_CTR 0x2190
+#define _REG_VCS_WATCHDOG_CTR 0x12178
+#define _REG_VCS_WATCHDOG_THRSH 0x1217C
+#define _REG_BCS_EIR 0x220B0
+#define _REG_BCS_EMR 0x220B4
+#define _REG_BCS_ESR 0x220B8
+#define _REG_VCS_EIR 0x120B0
+#define _REG_VCS_EMR 0x120B4
+#define _REG_VCS_ESR 0x120B8
+#define _REG_VECS_EIR 0x1A0B0
+#define _REG_VECS_EMR 0x1A0B4
+#define _REG_VECS_ESR 0x1A0B8
+
+/* blacklight PWM control */
+#define _REG_HISTOGRAM_THRSH 0x48268
+#define _REGBIT_HISTOGRAM_IRQ_ENABLE (1 << 31)
+#define _REGBIT_HISTOGRAM_IRQ_STATUS (1 << 30)
+
+/*
+ * Configuration register definition for BDF: 0:0:0.
+ */
+#define _REG_GMCH_CONTRL 0x50
+#define _REGBIT_SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */
+#define _REGBIT_SNB_GMCH_GMS_MASK 0x1f
+#define _REGBIT_BDW_GMCH_GMS_SHIFT 8
+#define _REGBIT_BDW_GMCH_GMS_MASK 0xff
+
+/* HSW */
+#define _REGBIT_SPLL_CTL_ENABLE (1 << 31)
+
+#define _REG_PORT_CLK_SEL_DDIC 0x46108
+#define _REG_PORT_CLK_SEL_DDID 0x4610C
+#define _REG_PORT_CLK_SEL_DDIE 0x46110
+
+#define _REG_TRANS_CLK_SEL_C 0x46148
+#define SBI_RESPONSE_MASK 0x3
+#define SBI_RESPONSE_SHIFT 0x1
+#define SBI_STAT_MASK 0x1
+#define SBI_STAT_SHIFT 0x0
+#define SBI_OPCODE_SHIFT 8
+#define SBI_OPCODE_MASK (0xff << SBI_OPCODE_SHIFT)
+#define SBI_CMD_IORD 2
+#define SBI_CMD_IOWR 3
+#define SBI_CMD_CRRD 6
+#define SBI_CMD_CRWR 7
+#define SBI_ADDR_OFFSET_SHIFT 16
+#define SBI_ADDR_OFFSET_MASK (0xffff << SBI_ADDR_OFFSET_SHIFT)
+
#define _GVT_TRANS_DDI_FUNC_CTL(tran) _TRANS(tran, _TRANS_DDI_FUNC_CTL_A, \
_TRANS_DDI_FUNC_CTL_B)
+/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
+#define _TRANS_DDI_MODE_SELECT_HIFT 24
+#define _TRANS_DDI_EDP_INPUT_SHIFT 12
+
+#define _REG_GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
+
+#define _REG_PIPE_WM_LINETIME_C 0x45278
+
+#define _REG_HSW_VIDEO_DIP_CTL_C 0x62200
+#define _REG_HSW_VIDEO_DIP_CTL_EDP 0x6F200
+
+/* GEN8 interrupt registers definations */
+#define _REG_GT_ISR(which) (0x44300 + (0x10 * (which)))
+#define _REG_GT_IMR(which) (0x44304 + (0x10 * (which)))
+#define _REG_GT_IIR(which) (0x44308 + (0x10 * (which)))
+#define _REG_GT_IER(which) (0x4430c + (0x10 * (which)))
+
+#define _REG_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
+#define _REG_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
+#define _REG_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
+#define _REG_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
+
+#define _REG_RING_PDP_UDW(base, n) (base + 0x270 + ((n) * 8 + 4))
+#define _REG_RING_PDP_LDW(base, n) (base + 0x270 + (n) * 8)
+
+#define _REG_RCS_PDP_UDW(n) _REG_RING_PDP_UDW(0x2000, n)
+#define _REG_RCS_PDP_LDW(n) _REG_RING_PDP_LDW(0x2000, n)
+
+#define _REG_VCS_PDP_UDW(n) _REG_RING_PDP_UDW(0x12000, n)
+#define _REG_VCS_PDP_LDW(n) _REG_RING_PDP_LDW(0x12000, n)
+
+#define _REG_VCS2_PDP_UDW(n) _REG_RING_PDP_UDW(0x1c000, n)
+#define _REG_VCS2_PDP_LDW(n) _REG_RING_PDP_LDW(0x1c000, n)
+
+#define _REG_VECS_PDP_UDW(n) _REG_RING_PDP_UDW(0x1a000, n)
+#define _REG_VECS_PDP_LDW(n) _REG_RING_PDP_LDW(0x1a000, n)
+
+#define _REG_BCS_PDP_UDW(n) _REG_RING_PDP_UDW(0x22000, n)
+#define _REG_BCS_PDP_LDW(n) _REG_RING_PDP_LDW(0x22000, n)
+
#endif
--
1.9.1
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