So I have no real justification for this. It does seem to help a bit though. It all kinda looks like a fifo underrun due to bad watermarks, but the fifo underruns definitely start to happen way before we enable the first plane. And the 4 additional vblanks are also not really perfect in stopping them, so it all seems fairly random. The IIR clearing was just a side trail, assuming that somehow we had old underruns stuck somewhere in the 2-deep queue. Didn't seem to help. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93787 Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx> --- drivers/gpu/drm/i915/i915_irq.c | 8 ++++++++ drivers/gpu/drm/i915/intel_display.c | 9 ++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 25a89373df63..bbc4d1b1dc67 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -236,6 +236,10 @@ void ilk_update_display_irq(struct drm_i915_private *dev_priv, dev_priv->irq_mask = new_val; I915_WRITE(DEIMR, dev_priv->irq_mask); POSTING_READ(DEIMR); + I915_WRITE(DEIIR, dev_priv->irq_mask); + POSTING_READ(DEIIR); + I915_WRITE(DEIIR, dev_priv->irq_mask); + POSTING_READ(DEIIR); } } @@ -492,6 +496,10 @@ void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, I915_WRITE(SDEIMR, sdeimr); POSTING_READ(SDEIMR); + I915_WRITE(SDEIIR, sdeimr); + POSTING_READ(SDEIIR); + I915_WRITE(SDEIIR, sdeimr); + POSTING_READ(SDEIIR); } static void diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8104511ad302..068504011b73 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4181,7 +4181,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) intel_fdi_normal_train(crtc); - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); + intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, !IS_GEN5(dev)); /* For PCH DP, enable TRANS_DP_CTL */ if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { @@ -4930,6 +4930,13 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) /* Must wait for vblank to avoid spurious PCH FIFO underruns */ if (intel_crtc->config->has_pch_encoder) intel_wait_for_vblank(dev, pipe); + if (IS_GEN5(dev)) { + intel_wait_for_vblank(dev, pipe); + intel_wait_for_vblank(dev, pipe); + intel_wait_for_vblank(dev, pipe); + intel_wait_for_vblank(dev, pipe); + intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); + } intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); intel_fbc_enable(intel_crtc); -- 2.5.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
