Re: [PATCH] drm/i915: Remove obsolete starting offset from struct i915_address_space

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On Fri, Jan 15, 2016 at 11:57:49AM +0000, Chris Wilson wrote:
> Since the removal of UMS, we have always had sole ownership of the GTTs.
> We no longer have to track the subsection we are allowed to use (denoted
> by start + total). vGPU does restrict the range of the global GTT we can
> use (as it has to share it amongst all the clients on the host), but
> that is achieved by ballooning reserved node within the whole (so that
> it could adjust available space dynamically). As such
> i915_address_space.start is always 0 and we can remove having to worry
> about such complications.
> 
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: Dave Gordon <david.s.gordon@xxxxxxxxx>
> Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>

Reviewed-by: Daniel Vetter <daniel.vetter@xxxxxxxx>

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c |  2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 24 ++++++++----------------
>  drivers/gpu/drm/i915/i915_gem_gtt.h |  1 -
>  drivers/gpu/drm/i915/i915_vgpu.c    | 17 +++++++----------
>  4 files changed, 16 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index e3377abc0d4d..b1bd710f645a 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -495,7 +495,7 @@ static int i915_gem_object_info(struct seq_file *m, void* data)
>  
>  	seq_printf(m, "%llu [%llu] gtt total\n",
>  		   dev_priv->gtt.base.total,
> -		   (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
> +		   dev_priv->gtt.mappable_end);
>  
>  	seq_putc(m, '\n');
>  	print_batch_pool_stats(m, dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 56f4f2e58d53..11080f00bda1 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1443,7 +1443,7 @@ static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp,
>  static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
>  {
>  	struct i915_address_space *vm = &ppgtt->base;
> -	uint64_t start = ppgtt->base.start;
> +	uint64_t start = 0;
>  	uint64_t length = ppgtt->base.total;
>  	gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
>  						 I915_CACHE_LLC, true);
> @@ -1507,7 +1507,6 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
>  	if (ret)
>  		return ret;
>  
> -	ppgtt->base.start = 0;
>  	ppgtt->base.cleanup = gen8_ppgtt_cleanup;
>  	ppgtt->base.allocate_va_range = gen8_alloc_va_range;
>  	ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
> @@ -1560,7 +1559,7 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
>  	gen6_pte_t scratch_pte;
>  	uint32_t pd_entry;
>  	uint32_t  pte, pde, temp;
> -	uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
> +	uint32_t start = 0, length = ppgtt->base.total;
>  
>  	scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
>  				     I915_CACHE_LLC, true, 0);
> @@ -2086,7 +2085,6 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
>  	ppgtt->base.unbind_vma = ppgtt_unbind_vma;
>  	ppgtt->base.bind_vma = ppgtt_bind_vma;
>  	ppgtt->base.cleanup = gen6_ppgtt_cleanup;
> -	ppgtt->base.start = 0;
>  	ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
>  	ppgtt->debug_dump = gen6_dump_ppgtt;
>  
> @@ -2123,7 +2121,7 @@ static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
>  static void i915_address_space_init(struct i915_address_space *vm,
>  				    struct drm_i915_private *dev_priv)
>  {
> -	drm_mm_init(&vm->mm, vm->start, vm->total);
> +	drm_mm_init(&vm->mm, 0, vm->total);
>  	vm->dev = dev_priv->dev;
>  	INIT_LIST_HEAD(&vm->active_list);
>  	INIT_LIST_HEAD(&vm->inactive_list);
> @@ -2312,8 +2310,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
>  	i915_check_and_clear_faults(dev);
>  
>  	dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
> -				       dev_priv->gtt.base.start,
> -				       dev_priv->gtt.base.total,
> +				       0, dev_priv->gtt.base.total,
>  				       true);
>  
>  	i915_ggtt_flush(dev_priv);
> @@ -2681,7 +2678,6 @@ static void i915_gtt_color_adjust(struct drm_mm_node *node,
>  }
>  
>  static int i915_gem_setup_global_gtt(struct drm_device *dev,
> -				     u64 start,
>  				     u64 mappable_end,
>  				     u64 end)
>  {
> @@ -2703,11 +2699,9 @@ static int i915_gem_setup_global_gtt(struct drm_device *dev,
>  
>  	BUG_ON(mappable_end > end);
>  
> -	ggtt_vm->start = start;
> -
>  	/* Subtract the guard page before address space initialization to
>  	 * shrink the range used by drm_mm */
> -	ggtt_vm->total = end - start - PAGE_SIZE;
> +	ggtt_vm->total = end - PAGE_SIZE;
>  	i915_address_space_init(ggtt_vm, dev_priv);
>  	ggtt_vm->total += PAGE_SIZE;
>  
> @@ -2773,8 +2767,7 @@ static int i915_gem_setup_global_gtt(struct drm_device *dev,
>  		}
>  
>  		ppgtt->base.clear_range(&ppgtt->base,
> -					ppgtt->base.start,
> -					ppgtt->base.total,
> +					0, ppgtt->base.total,
>  					true);
>  
>  		dev_priv->mm.aliasing_ppgtt = ppgtt;
> @@ -2793,7 +2786,7 @@ void i915_gem_init_global_gtt(struct drm_device *dev)
>  	gtt_size = dev_priv->gtt.base.total;
>  	mappable_size = dev_priv->gtt.mappable_end;
>  
> -	i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
> +	i915_gem_setup_global_gtt(dev, mappable_size, gtt_size);
>  }
>  
>  void i915_global_gtt_cleanup(struct drm_device *dev)
> @@ -3212,8 +3205,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
>  
>  	/* First fill our portion of the GTT with scratch pages */
>  	dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
> -				       dev_priv->gtt.base.start,
> -				       dev_priv->gtt.base.total,
> +				       0, dev_priv->gtt.base.total,
>  				       true);
>  
>  	/* Cache flush objects bound into GGTT and rebind them. */
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index b448ad832dcf..824dd966e5e4 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -273,7 +273,6 @@ struct i915_address_space {
>  	struct drm_mm mm;
>  	struct drm_device *dev;
>  	struct list_head global_link;
> -	u64 start;		/* Start offset always 0 for dri2 */
>  	u64 total;		/* size addr space maps (ex. 2GB for ggtt) */
>  
>  	struct i915_page_scratch *scratch_page;
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
> index dea7429be4d0..81054c8fdc26 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -182,7 +182,7 @@ int intel_vgt_balloon(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
> -	unsigned long ggtt_vm_end = ggtt_vm->start + ggtt_vm->total;
> +	unsigned long ggtt_vm_end = ggtt_vm->total;
>  
>  	unsigned long mappable_base, mappable_size, mappable_end;
>  	unsigned long unmappable_base, unmappable_size, unmappable_end;
> @@ -202,8 +202,7 @@ int intel_vgt_balloon(struct drm_device *dev)
>  	DRM_INFO("Unmappable graphic memory: base 0x%lx size %ldKiB\n",
>  		 unmappable_base, unmappable_size / 1024);
>  
> -	if (mappable_base < ggtt_vm->start ||
> -	    mappable_end > dev_priv->gtt.mappable_end ||
> +	if (mappable_end > dev_priv->gtt.mappable_end ||
>  	    unmappable_base < dev_priv->gtt.mappable_end ||
>  	    unmappable_end > ggtt_vm_end) {
>  		DRM_ERROR("Invalid ballooning configuration!\n");
> @@ -235,14 +234,12 @@ int intel_vgt_balloon(struct drm_device *dev)
>  	}
>  
>  	/* Mappable graphic memory ballooning */
> -	if (mappable_base > ggtt_vm->start) {
> -		ret = vgt_balloon_space(&ggtt_vm->mm,
> -					&bl_info.space[0],
> -					ggtt_vm->start, mappable_base);
> +	ret = vgt_balloon_space(&ggtt_vm->mm,
> +				&bl_info.space[0],
> +				0, mappable_base);
>  
> -		if (ret)
> -			goto err;
> -	}
> +	if (ret)
> +		goto err;
>  
>  	if (mappable_end < dev_priv->gtt.mappable_end) {
>  		ret = vgt_balloon_space(&ggtt_vm->mm,
> -- 
> 2.7.0.rc3
> 
> _______________________________________________
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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