On Tue, Jan 19, 2016 at 10:13:43AM -0800, Yu Dai wrote:
> Thanks for capture the typo. LGTM.
>
> Reviewed-by: Alex Dai <yu.dai@xxxxxxxxx>
>
> On 01/18/2016 07:59 AM, Arun Siluvery wrote:
> >In GuC submission mode, driver has to provide a list of registers to be
> >save/restored during gpu reset, make the max no. of registers value consistent
> >with that of the value defined in FW. If they are not in sync then register
> >save/restore during gpu reset won't work as expected.
> >
> >Cc: Alex Dai <yu.dai@xxxxxxxxx>
> >Cc: Dave Gordon <david.s.gordon@xxxxxxxxx>
> >Signed-off-by: Arun Siluvery <arun.siluvery@xxxxxxxxxxxxxxx>
Queued for -next, thanks for the patch.
-Daniel
> >---
> > drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> >index 130d94c..1d8048b 100644
> >--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> >+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> >@@ -370,7 +370,7 @@ struct guc_policies {
> > #define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8
> > #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10
> >-#define GUC_REGSET_MAX_REGISTERS 20
> >+#define GUC_REGSET_MAX_REGISTERS 25
> > #define GUC_MMIO_WHITE_LIST_START 0x24d0
> > #define GUC_MMIO_WHITE_LIST_MAX 12
> > #define GUC_S3_SAVE_SPACE_PAGES 10
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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