On Thu, 14 Jan 2016, Francisco Jerez <currojerez@xxxxxxxxxx> wrote: > Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx> writes: > >> On Thu, 14 Jan 2016, Francisco Jerez <currojerez@xxxxxxxxxx> wrote: >>> We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee >>> that writes performed via the HDC are visible in memory. Fixes an >>> intermittent failure in a Piglit test that writes to a BO from a >>> shader using GL atomic counters (implemented as HDC untyped atomics) >>> and then expects the memory to read back the same value after mapping >>> it on the CPU. >>> >>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298 >>> Tested-by: Mark Janes <mark.a.janes@xxxxxxxxx> >>> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> >> >> Francisco, this is missing your Signed-off-by i.e. developer certificate >> of origin http://developercertificate.org/ - can't push without. Please >> reply with that. >> > Oops, sorry for that -- And yeah it shouldn't hurt to CC stable too. > > Signed-off-by: Francisco Jerez <currojerez@xxxxxxxxxx> Pushed to drm-intel-next-queued, thanks for the patch and review. BR, Jani. > >> BR, >> Jani. >> >> >>> --- >>> drivers/gpu/drm/i915/intel_lrc.c | 1 + >>> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++ >>> 2 files changed, 3 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c >>> index ab344e0..02213c6 100644 >>> --- a/drivers/gpu/drm/i915/intel_lrc.c >>> +++ b/drivers/gpu/drm/i915/intel_lrc.c >>> @@ -1735,6 +1735,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request, >>> if (flush_domains) { >>> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; >>> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; >>> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; >>> flags |= PIPE_CONTROL_FLUSH_ENABLE; >>> } >>> >>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c >>> index 4060acf..8cd8aab 100644 >>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c >>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c >>> @@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req, >>> if (flush_domains) { >>> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; >>> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; >>> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; >>> flags |= PIPE_CONTROL_FLUSH_ENABLE; >>> } >>> if (invalidate_domains) { >>> @@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req, >>> if (flush_domains) { >>> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; >>> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; >>> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; >>> flags |= PIPE_CONTROL_FLUSH_ENABLE; >>> } >>> if (invalidate_domains) { >> >> -- >> Jani Nikula, Intel Open Source Technology Center -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
