Reviewed-by: Alex Dai <yu.dai@xxxxxxxxx>
On 01/08/2016 07:03 AM, Peter Antoine wrote:
Per-context initialisation GPU instructions (which are injected directly
into the ringbuffer rather than being submitted as a batch) should not
be allowed to mix with user-generated batches in the same submission; it
will cause confusion for the GuC (which might merge a subsequent
preemptive request with the non-preemptive initialisation code), and for
the scheduler, which wouldn't know how to re-inject a non-batch request
if it were the victim of preemption.
Therefore, we should wait for the initialisation request to complete
before making the newly-initialised context available for user-mode
submissions.
Here, we add a call to i915_wait_request() after each existing call to
i915_add_request_no_flush() (in i915_gem_init_hw(), for the default
per-engine contexts, and intel_lr_context_deferred_create(), for all
others).
Adapted from Dave Gordon's patch, which is adapted from Alex's earlier
patch, which added the wait only to intel_lr_context_render_state_init().
Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
Signed-off-by: Dave Gordon <david.s.gordon@xxxxxxxxx>
Signed-off-by: Peter Antoine <peter.antoine@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_gem.c | 10 ++++++++++
drivers/gpu/drm/i915/intel_lrc.c | 11 +++++++++++
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5be4433..e71bf90 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4847,6 +4847,16 @@ i915_gem_init_hw(struct drm_device *dev)
}
i915_add_request_no_flush(req);
+
+ /*
+ * GuC firmware will try to collapse its DPC work queue if the
+ * new one is for same context. So the following breadcrumb
+ * could be amended to this batch and submitted as one batch.
+ * Wait here to make sure the context state init is finished
+ * before any other submission to GuC.
+ */
+ if (i915.enable_guc_submission)
+ ret = i915_wait_request(req);
}
out:
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3aa6147..f18fb11 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2499,6 +2499,17 @@ int intel_lr_context_deferred_alloc(struct intel_context *ctx,
goto error_ringbuf;
}
i915_add_request_no_flush(req);
+
+ /*
+ * GuC firmware will try to collapse its DPC work queue
+ * if the new one is for same context. So the
+ * following breadcrumb could be amended to this batch
+ * and submitted as one batch. Wait here to make sure
+ * the context state init is finished before any other
+ * submission to GuC.
+ */
+ if (i915.enable_guc_submission)
+ ret = i915_wait_request(req);
}
return 0;
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