On Mon, Jan 11, 2016 at 11:39:27AM +0000, Michel Thierry wrote: > Kernel and userspace are able to handle 4GB (1<<32) address space range, > but "A32 Stateless Model" is not. According to documentation, A32 accesses > are based on General State Base Address and bound checking is in place. > Because size field (instruction State Base Address) limitation, it is not > possible to address full 4GB memory region. > > A32 Stateless Model is used by some libraries and without this patch, the > last page of 4GB address space is not accessible in 32bit processes. > > Reported-by: Artur Harasimiuk <artur.harasimiuk@xxxxxxxxx> > Signed-off-by: Michel Thierry <michel.thierry@xxxxxxxxx> That seems reasonably in line with the flag, and a caveat I think we live with (GGTT which is already 4G max can't use the last page, even if we hadn't already given it away). > --- > drivers/gpu/drm/i915/i915_gem.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 6c60e04..ddc21d4 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -3488,7 +3488,7 @@ i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, > if (flags & PIN_MAPPABLE) > end = min_t(u64, end, dev_priv->gtt.mappable_end); > if (flags & PIN_ZONE_4G) > - end = min_t(u64, end, (1ULL << 32)); > + end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); Bah, I came here expecting to find a mistake with brackets and u64 promotion. Spoilsport. Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
