Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> writes: > The workarounds for disabling hdc invalidation and also forcing > context to be non coherent, are advised to be used up until rev D0. > > However as it was found that rev F0, without the > WaForceEnableNonCoherent might system hang if the mesa > tried to use coherent mode. > > As these two workarounds are about non coherent access, are > grouped in scope and they point the same HSD, increase the > scope of both to set default behaviour to non coherent access. > > References: HSD: gen9lp/2131413 > References: http://lists.freedesktop.org/archives/mesa-dev/2015-November/101515.html > Cc: Ben Widawsky <benjamin.widawsky@xxxxxxxxx> > Cc: Francisco Jerez <currojerez@xxxxxxxxxx> > Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index eefce9a3e9c8..339701d7a9a5 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -1018,10 +1018,6 @@ static int skl_init_workarounds(struct intel_engine_cs *ring) > return ret; > > if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) { > - /* WaDisableHDCInvalidation:skl */ > - I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | > - BDW_DISABLE_HDC_INVALIDATION); > - > /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ > I915_WRITE(FF_SLICE_CS_CHICKEN2, > _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); > @@ -1046,7 +1042,7 @@ static int skl_init_workarounds(struct intel_engine_cs *ring) > WA_SET_BIT_MASKED(HIZ_CHICKEN, > BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); > > - if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) { > + if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) { > /* > *Use Force Non-Coherent whenever executing a 3D context. This > * is a workaround for a possible hang in the unlikely event > @@ -1055,6 +1051,10 @@ static int skl_init_workarounds(struct intel_engine_cs *ring) > /* WaForceEnableNonCoherent:skl */ > WA_SET_BIT_MASKED(HDC_CHICKEN0, > HDC_FORCE_NON_COHERENT); > + > + /* WaDisableHDCInvalidation:skl */ > + I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | > + BDW_DISABLE_HDC_INVALIDATION); Looks good to me, Reviewed-by: Francisco Jerez <currojerez@xxxxxxxxxx> > } > > /* WaBarrierPerformanceFixDisable:skl */ > -- > 2.5.0
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