I gave a try to this patch on Braswell.
A couple of comments below.
On 03/12/15 11:36, Shashank Sharma wrote:
CHV/BSW supports Degamma color correction, which linearizes all
the non-linear color values. This will be applied before Color
Transformation.
This patch does the following:
1. Attach deGamma property to CRTC
2. Add the core function to program DeGamma correction values for
CHV/BSW platform
2. Add DeGamma correction macros/defines
Signed-off-by: Shashank Sharma <shashank.sharma@xxxxxxxxx>
Signed-off-by: Kausal Malladi <kausalmalladi@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_color_manager.c | 95 ++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_color_manager.h | 5 ++
3 files changed, 106 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6259537..665e23e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8166,4 +8166,10 @@ enum skl_disp_power_wells {
#define _PIPE_GAMMA_BASE(pipe) \
(_PIPE3(pipe, PIPEA_CGM_GAMMA, PIPEB_CGM_GAMMA, PIPEC_CGM_GAMMA))
+#define PIPEA_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
+#define PIPEB_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
+#define PIPEC_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x6A000)
+#define _PIPE_DEGAMMA_BASE(pipe) \
+ (_PIPE3(pipe, PIPEA_CGM_DEGAMMA, PIPEB_CGM_DEGAMMA, PIPEC_CGM_DEGAMMA))
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c
index f4334c0..aa89a55 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -27,6 +27,95 @@
#include "intel_color_manager.h"
+static int chv_set_degamma(struct drm_device *dev,
+ struct drm_property_blob *blob, struct drm_crtc *crtc)
+{
+ u16 red_fract, green_fract, blue_fract;
+ u32 red, green, blue;
+ u32 num_samples;
+ u32 word = 0;
+ u32 count, cgm_control, cgm_degamma_reg;
+ i915_reg_t val;
+ enum pipe pipe;
+ struct drm_palette *degamma_data;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_r32g32b32 *correction_values = NULL;
+ struct drm_crtc_state *state = crtc->state;
+
+ if (WARN_ON(!blob))
+ return -EINVAL;
+
+ degamma_data = (struct drm_palette *)blob->data;
+ pipe = to_intel_crtc(crtc)->pipe;
+ num_samples = blob->length / sizeof(struct drm_r32g32b32);
+
+ switch (num_samples) {
+ case GAMMA_DISABLE_VALS:
+ /* Disable DeGamma functionality on Pipe - CGM Block */
+ val = _MMIO(_PIPE_CGM_CONTROL(pipe));
+ cgm_control = I915_READ(val);
+ cgm_control &= ~CGM_DEGAMMA_EN;
+ state->palette_before_ctm_blob = NULL;
+
+ I915_WRITE(val, cgm_control);
+ DRM_DEBUG_DRIVER("DeGamma disabled on Pipe %c\n",
+ pipe_name(pipe));
+ break;
+
+ case CHV_DEGAMMA_MAX_VALS:
+ cgm_degamma_reg = _PIPE_DEGAMMA_BASE(pipe);
+ count = 0;
+ correction_values = (struct drm_r32g32b32 *)°amma_data->lut;
The line above is incorrect. This is reading from an invalid memory address.
Just use this :
correction_values = degamma_data->lut;
+ while (count < CHV_DEGAMMA_MAX_VALS) {
+ blue = correction_values[count].b32;
+ green = correction_values[count].g32;
+ red = correction_values[count].r32;
+
+ if (blue > CHV_MAX_GAMMA)
+ blue = CHV_MAX_GAMMA;
+
+ if (green > CHV_MAX_GAMMA)
+ green = CHV_MAX_GAMMA;
+
+ if (red > CHV_MAX_GAMMA)
+ red = CHV_MAX_GAMMA;
+
+ blue_fract = GET_BITS(blue, 8, 14);
+ green_fract = GET_BITS(green, 8, 14);
+ red_fract = GET_BITS(red, 8, 14);
This is reading the wrong bits from the blob here.
Using your macro, it should be :
blue_fract = GET_BITS(blue, 10, 14);
green_fract = GET_BITS(green, 10, 14);
red_fract = GET_BITS(red, 10, 14);
+
+ /* Green (29:16) and Blue (13:0) in DWORD1 */
+ SET_BITS(word, green_fract, 16, 14);
+ SET_BITS(word, blue_fract, 0, 14);
+ val = _MMIO(cgm_degamma_reg);
+ I915_WRITE(val, word);
+ cgm_degamma_reg += 4;
+
+ /* Red (13:0) to be written to DWORD2 */
+ word = red_fract;
+ val = _MMIO(cgm_degamma_reg);
+ I915_WRITE(val, word);
+ cgm_degamma_reg += 4;
+ count++;
+ }
+
+ DRM_DEBUG_DRIVER("DeGamma LUT loaded for Pipe %c\n",
+ pipe_name(pipe));
+
+ /* Enable DeGamma on Pipe */
+ val = _MMIO(_PIPE_CGM_CONTROL(pipe));
+ I915_WRITE(val, I915_READ(val) | CGM_DEGAMMA_EN);
+ DRM_DEBUG_DRIVER("DeGamma correction enabled on Pipe %c\n",
+ pipe_name(pipe));
+ break;
+
+ default:
+ DRM_ERROR("Invalid number of samples for DeGamma LUT\n");
+ return -EINVAL;
+ }
+ return 0;
+}
+
static int chv_set_gamma(struct drm_device *dev, struct drm_property_blob *blob,
struct drm_crtc *crtc)
{
@@ -158,4 +247,10 @@ void intel_attach_color_properties_to_crtc(struct drm_device *dev,
DRM_DEBUG_DRIVER("gamma property attached to CRTC\n");
}
+ /* Degamma correction */
+ if (config->cm_palette_before_ctm_property) {
+ drm_object_attach_property(mode_obj,
+ config->cm_palette_before_ctm_property, 0);
+ DRM_DEBUG_DRIVER("degamma property attached to CRTC\n");
+ }
}
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h
index de706d9..77a2119 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -63,5 +63,10 @@
#define CHV_GAMMA_SHIFT_GREEN 16
#define CHV_MAX_GAMMA ((1 << 24) - 1)
+/* Degamma on CHV */
+#define CHV_DEGAMMA_MSB_SHIFT 2
+#define CHV_DEGAMMA_GREEN_SHIFT 16
+
/* CHV CGM Block */
#define CGM_GAMMA_EN (1 << 2)
+#define CGM_DEGAMMA_EN (1 << 0)
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