On Mon, Dec 14, 2015 at 09:52:10PM +0000, Chris Wilson wrote: > On Mon, Dec 14, 2015 at 10:15:51PM +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote: > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > Gen2/3 platforms have some unusual tile dimensions. Account > > for them to make the test work correctly. > > iirc, for the purposes of the test, we could just set the stride to 512 > and be done with it. The idea behind the test is to simply require a > fence register and then since we compare the same tiling pattern in > both, the actual tiling is irrevelant. (I wonder if using different > strides is of any value, not sure that it is - it doesn't change any > code paths). Well, it definitely didn't work with 512 for the X tiled. Let's see. 512 bytes is four tiles horizontally on gen2, but we only allocate two tiles for the object (4k). Then we walk over the mapping meaning we first hit 128 bytes of the first tile, then 128 bytes of the second tile. Then we walk into oblivion, which I suppose means the scratch page. So we do that until we've written 4k bytes, meaning we only manage to write something to the top halves of the two tiles we actually allocated. -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
