On Tue, Dec 15, 2015 at 07:45:42PM +0200, Mika Kuoppala wrote: > Imre mentioned that chv might also have capability to > track unclaimed mmio accesses. Ville added that > both chv and vlv has this capability and he had already > made this way back [1]. Mimic what Ville's patch does > but adapt on top of less frequent mmio accesses by > omitting checking always on reg writes. > > This patch is untested as of now. > > v2: overflow handling and posting omitted (Ville) > > References: [1] http://lists.freedesktop.org/archives/intel-gfx/2013-May/027599.html > Cc: Imre Deak <imre.deak@xxxxxxxxx> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> lgtm Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_reg.h | 5 +++++ > drivers/gpu/drm/i915/intel_uncore.c | 31 +++++++++++++++++++++++++++---- > 2 files changed, 32 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 007ae83..0a98889 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1711,6 +1711,11 @@ enum skl_disp_power_wells { > #define FPGA_DBG _MMIO(0x42300) > #define FPGA_DBG_RM_NOCLAIM (1<<31) > > +#define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) > +#define CLAIM_ER_CLR (1 << 31) > +#define CLAIM_ER_OVERFLOW (1 << 16) > +#define CLAIM_ER_CTR_MASK 0xffff > + > #define DERRMR _MMIO(0x44050) > /* Note that HBLANK events are reserved on bdw+ */ > #define DERRMR_PIPEA_SCANLINE (1<<0) > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index b6910eb..61179ae 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -335,13 +335,10 @@ static void intel_uncore_ellc_detect(struct drm_device *dev) > } > > static bool > -check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) > +fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) > { > u32 dbg; > > - if (!HAS_FPGA_DBG_UNCLAIMED(dev_priv)) > - return false; > - > dbg = __raw_i915_read32(dev_priv, FPGA_DBG); > if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM))) > return false; > @@ -351,6 +348,32 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) > return true; > } > > +static bool > +vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) > +{ > + u32 cer; > + > + cer = __raw_i915_read32(dev_priv, CLAIM_ER); > + if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK)))) > + return false; > + > + __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR); > + > + return true; > +} > + > +static bool > +check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) > +{ > + if (HAS_FPGA_DBG_UNCLAIMED(dev_priv)) > + return fpga_check_for_unclaimed_mmio(dev_priv); > + > + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > + return vlv_check_for_unclaimed_mmio(dev_priv); > + > + return false; > +} > + > static void __intel_uncore_early_sanitize(struct drm_device *dev, > bool restore_forcewake) > { > -- > 2.5.0 -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
