On Tue, Dec 15, 2015 at 01:05:56PM +0200, Ville Syrjälä wrote: > On Tue, Dec 15, 2015 at 10:24:13AM +0000, Chris Wilson wrote: > > The other question, does this obsolete our work around? Can I be that > > optimisitic? > > The CS TLB one? I think I tried it at some point, and things till > failed. But stuff fails even with the w/a (like I said piglit will > hang the GPU eventually), so I can't be sure that I actually tested > the CS TLB fail. I think I need to retest at some point. > > As far as the docs go, I only remember it mentioning some TLB fail > affecting the blitter. I guess the CS TLB fail isn't actually > documented anywhere? It's hard to be sure since the issue is only mentioned obliquely in bspec. I strongly suspect there is only one set of TLB on the device, so I think it is the same. But I never did figure out what flush they meant, as all the chipset or MI level flushes never seemed to do anything to improve the situation. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
