On Tue, Dec 08, 2015 at 11:07:01PM +0200, Ville Syrjälä wrote: > On Tue, Dec 08, 2015 at 08:50:48PM +0000, Chris Wilson wrote: > > On Tue, Dec 08, 2015 at 07:45:50PM +0200, Ville Syrjälä wrote: > > > On Tue, Dec 08, 2015 at 09:38:52AM -0800, Wayne Boyer wrote: > > > > Do some further clean up based on the initial review of > > > > drm/i915: Separate cherryview from valleyview. > > > > > > > > In this case, in i915_gem_alloc_context_obj() only call > > > > i915_gem_object_set_cache_level() for Ivy Bridge devices > > > > since later platforms don't have L3 control bits in the PTE. > > > > > > > > v2: Expand comment to mention snooping requirement. (Ville, Imre) > > > > > > > > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > > > > Signed-off-by: Wayne Boyer <wayne.boyer@xxxxxxxxx> > > > > > > Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > Loses Haswell. > > Nope. HSW doesn't do L3 via PTEs. I was actually thinking of eLLC, but we never differentiate that bit in our cache levels. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
