On Fri, Dec 04, 2015 at 04:25:19PM +0000, Deepak, M wrote: > > > > -----Original Message----- > > From: Daniel Vetter [mailto:daniel.vetter@xxxxxxxx] On Behalf Of Daniel > > Vetter > > Sent: Friday, December 4, 2015 9:52 PM > > To: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Cc: Deepak, M <m.deepak@xxxxxxxxx>; intel-gfx@xxxxxxxxxxxxxxxxxxxxx > > Subject: Re: [PATCH 2/3] drm/i915: Correct the Ref clock value for > > BXT > > > > On Fri, Dec 04, 2015 at 11:55:56AM +0200, Ville Syrjälä wrote: > > > On Fri, Dec 04, 2015 at 07:47:38PM +0530, Deepak M wrote: > > > > The reference clock for BXT is 19.2 MHz not 19.5 MHz, updating the > > > > correct value here. > > > > > > > > Signed-off-by: Deepak M <m.deepak@xxxxxxxxx> > > > > --- > > > > drivers/gpu/drm/i915/i915_reg.h | 2 +- > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > > > b/drivers/gpu/drm/i915/i915_reg.h index 8bd2699..009f474 100644 > > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > > @@ -7676,7 +7676,7 @@ enum skl_disp_power_wells { > > > > #define BXT_DSI_PLL_RATIO_MAX 0x7D > > > > #define BXT_DSI_PLL_RATIO_MIN 0x22 > > > > #define BXT_DSI_PLL_RATIO_MASK 0xFF > > > > -#define BXT_REF_CLOCK_KHZ 19500 > > > > +#define BXT_REF_CLOCK_KHZ 19200 > > > > > > No idea why we have this define in i915_reg.h. We don't have such > > > defines for other platforms (also my fix CHV refclk to 19.2MHz patch > > > never got reviewed by anyone either. Interedted?) > > > > Add link and I think Deepak is volunteered ;-) > > > > [Deepak, M] Please share the link, I can go through the patch :) This is the whole series: http://lists.freedesktop.org/archives/intel-gfx/2015-September/075097.html Some of it might have bitrotted a bit, but nothing a rebase wouldn't fix I think. There's also this other patch dealing with dual-link (which I've never tested due to lack of hardware): http://lists.freedesktop.org/archives/intel-gfx/2015-September/075568.html > > > > Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > Queued for -next, thanks for the patch. > > -Daniel > > > > > > > > > > > #define BXT_DSI_PLL_ENABLE 0x46080 > > > > #define BXT_DSI_PLL_DO_ENABLE (1 << 31) > > > > -- > > > > 1.9.1 > > > > > > > > _______________________________________________ > > > > Intel-gfx mailing list > > > > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > > > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > > -- > > > Ville Syrjälä > > > Intel OTC > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > > Daniel Vetter > > Software Engineer, Intel Corporation > > http://blog.ffwll.ch -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
