On Mon, 30 Nov 2015, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> CTG uses hrawclk for backlight, so calculate the max based on that
> instead of cdclk.
If you say so.
Acked-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> Fixes: aa17cdb4f836 ("drm/i915: initialize backlight max from VBT")
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_panel.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index ea528ca854e8..737e12349e81 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1344,13 +1344,19 @@ static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
>
> /*
> * Gen4: This value represents the period of the PWM stream in display core
> - * clocks multiplied by 128.
> + * clocks ([DevCTG] HRAW clocks) multiplied by 128.
> + *
> */
> static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
> {
> struct drm_device *dev = connector->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - int clock = 1000 * dev_priv->display.get_display_clock_speed(dev);
> + int clock;
> +
> + if (IS_G4X(dev_priv))
> + clock = MHz(intel_hrawclk(dev));
> + else
> + clock = 1000 * dev_priv->display.get_display_clock_speed(dev);
>
> return clock / (pwm_freq_hz * 128);
> }
--
Jani Nikula, Intel Open Source Technology Center
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