On Mon, Nov 23, 2015 at 06:06:17PM +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Pull the BDW+ DE pipe interrupt mask frobbing into a central place,
> like we have for other platforms.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 14 ++++++++++
> drivers/gpu/drm/i915/i915_irq.c | 41 +++++++++++++++++++++++++-----
> drivers/gpu/drm/i915/intel_fifo_underrun.c | 8 ++----
> 3 files changed, 51 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b9f86a73c543..c3330ff5016d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2762,6 +2762,20 @@ ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
> {
> ilk_update_display_irq(dev_priv, bits, 0);
> }
> +void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
> + enum pipe pipe,
> + uint32_t interrupt_mask,
> + uint32_t enabled_irq_mask);
> +static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
> + enum pipe pipe, uint32_t bits)
> +{
> + bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
> +}
> +static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
> + enum pipe pipe, uint32_t bits)
> +{
> + bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
> +}
> void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
> uint32_t interrupt_mask,
> uint32_t enabled_irq_mask);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 5aea557f3776..92389a9bb301 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -438,6 +438,38 @@ static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
> }
>
> /**
> + * bdw_update_pipe_irq - update DE pipe interrupt
> + * @dev_priv: driver private
> + * @pipe: pipe whose interrupt to update
> + * @interrupt_mask: mask of interrupt bits to update
> + * @enabled_irq_mask: mask of interrupt bits to enable
> + */
kerneldoc is aligned like
/**
*
*/
With that OCD in the OCD addressed:
Reviewed-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
> +void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
> + enum pipe pipe,
> + uint32_t interrupt_mask,
> + uint32_t enabled_irq_mask)
> +{
> + uint32_t new_val;
> +
> + assert_spin_locked(&dev_priv->irq_lock);
> +
> + WARN_ON(enabled_irq_mask & ~interrupt_mask);
> +
> + if (WARN_ON(!intel_irqs_enabled(dev_priv)))
> + return;
> +
> + new_val = dev_priv->de_irq_mask[pipe];
> + new_val &= ~interrupt_mask;
> + new_val |= (~enabled_irq_mask & interrupt_mask);
> +
> + if (new_val != dev_priv->de_irq_mask[pipe]) {
> + dev_priv->de_irq_mask[pipe] = new_val;
> + I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
> + POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
> + }
> +}
> +
> +/**
> * ibx_display_interrupt_update - update SDEIMR
> * @dev_priv: driver private
> * @interrupt_mask: mask of interrupt bits to update
> @@ -2658,10 +2690,9 @@ static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
> unsigned long irqflags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> - dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
> - I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
> - POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
> + bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +
> return 0;
> }
>
> @@ -2709,9 +2740,7 @@ static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
> unsigned long irqflags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> - dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
> - I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
> - POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
> + bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> index 48bd079bdb06..bda526660e20 100644
> --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> @@ -178,14 +178,10 @@ static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - assert_spin_locked(&dev_priv->irq_lock);
> -
> if (enable)
> - dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
> + bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
> else
> - dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
> - I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
> - POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
> + bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
> }
>
> static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
> --
> 2.4.10
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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