On Mon, Nov 23, 2015 at 02:16:40PM -0800, Rodrigo Vivi wrote:
> Whenever DMC firmware put the HW into DC State a bunch
> of registers including this perf counter is reset to 0.
>
> Even with PSR active and working we could still read
> "Performance_Counter: 0" what will misslead people to believe
> PSR is broken. For instance on SKL we can only see PC10
> residency with screen on if PSR is working properly.
> However Performance_Counter was showing 0.
>
> Even if it restored properly on DC6 exit we don't want to
> give users the wrong impression that PSR is not working
> while we know for sure it is.
>
> So, it is better to remove this counter information while
> we don't have a better way to track PSR residency.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Reviewed-by: Durgadoss R <durgadoss.r@xxxxxxxxx>
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index b28da6f..a728ff1 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2582,8 +2582,11 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
> }
> seq_puts(m, "\n");
>
> - /* CHV PSR has no kind of performance counter */
> - if (HAS_DDI(dev)) {
> + /*
> + * VLV/CHV PSR has no kind of performance counter
> + * SKL+ Perf counter is reset to 0 everytime DC state is entered
> + */
> + if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> psrperf = I915_READ(EDP_PSR_PERF_CNT) &
> EDP_PSR_PERF_CNT_MASK;
>
> --
> 2.4.3
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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