Now that pixel clock is set to 0 when there are no active pipes it's easy to set the bypass frequency for this case. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/intel_display.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 178a042f917e..8a825f24ce51 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5972,7 +5972,6 @@ static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, /* * FIXME: * - remove the guardband, it's not needed on BXT - * - set 19.2MHz bypass frequency if there are no active pipes */ if (max_pixclk > 576000*9/10) return 624000; @@ -5982,8 +5981,10 @@ static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, return 384000; else if (max_pixclk > 144000*9/10) return 288000; - else + else if (max_pixclk) return 144000; + else + return 19200; } /* Compute the max pixel clock for new configuration. Uses atomic state if -- 2.1.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
