From: Dave Gordon <david.s.gordon@xxxxxxxxx>
For: VIZ-2021
Signed-off-by: Dave Gordon <david.s.gordon@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 49 ++++++++++++------------------
drivers/gpu/drm/i915/intel_guc.h | 16 +++++-----
3 files changed, 28 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 1c1c4bd..fefe73c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2666,7 +2666,7 @@ static void i915_guc_client_info(struct seq_file *m,
seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
client->priority, client->ctx_index, client->proc_desc_offset);
seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
- client->doorbell_id, client->doorbell_offset, client->cookie);
+ client->doorbell_id, client->doorbell_offset, client->doorbell_cookie);
seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
client->wq_size, client->wq_offset, client->wq_tail);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 0a6b007..55e10eb 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -210,11 +210,11 @@ static int guc_ring_doorbell(struct i915_guc_client *gc)
/* current cookie */
db_cmp.db_status = GUC_DOORBELL_ENABLED;
- db_cmp.cookie = gc->cookie;
+ db_cmp.cookie = gc->doorbell_cookie;
/* cookie to be updated */
db_exc.db_status = GUC_DOORBELL_ENABLED;
- db_exc.cookie = gc->cookie + 1;
+ db_exc.cookie = gc->doorbell_cookie + 1;
if (db_exc.cookie == 0)
db_exc.cookie = 1;
@@ -229,7 +229,7 @@ static int guc_ring_doorbell(struct i915_guc_client *gc)
/* if the exchange was successfully executed */
if (db_ret.value_qw == db_cmp.value_qw) {
/* db was successfully rung */
- gc->cookie = db_exc.cookie;
+ gc->doorbell_cookie = db_exc.cookie;
ret = 0;
break;
}
@@ -385,7 +385,9 @@ static void guc_init_proc_desc(struct intel_guc *guc,
static void guc_init_ctx_desc(struct intel_guc *guc,
struct i915_guc_client *client)
{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct intel_context *ctx = client->owner;
+ struct intel_engine_cs *ring;
struct guc_context_desc desc;
struct sg_table *sg;
int i;
@@ -397,12 +399,10 @@ static void guc_init_ctx_desc(struct intel_guc *guc,
desc.priority = client->priority;
desc.db_id = client->doorbell_id;
- for (i = 0; i < I915_NUM_RINGS; i++) {
+ for_each_ring(ring, dev_priv, i) {
struct guc_execlist_context *lrc = &desc.lrc[i];
struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf;
- struct intel_engine_cs *ring;
- struct drm_i915_gem_object *obj;
- uint64_t ctx_desc;
+ struct drm_i915_gem_object *obj = ctx->engine[i].state;
/* TODO: We have a design issue to be solved here. Only when we
* receive the first batch, we know which engine is used by the
@@ -411,22 +411,16 @@ static void guc_init_ctx_desc(struct intel_guc *guc,
* for now who owns a GuC client. But for future owner of GuC
* client, need to make sure lrc is pinned prior to enter here.
*/
- obj = ctx->engine[i].state;
if (!obj)
- break; /* XXX: continue? */
-
- ring = ringbuf->ring;
- ctx_desc = intel_lr_context_descriptor(ctx, ring);
- lrc->context_desc = (u32)ctx_desc;
+ continue;
- /* The state page is after PPHWSP */
+ lrc->context_desc = (u32)intel_lr_context_descriptor(ctx, ring);
lrc->ring_lcra = i915_gem_obj_ggtt_offset(obj) +
- LRC_STATE_PN * PAGE_SIZE;
+ LRC_STATE_PN * PAGE_SIZE;
lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
- (ring->id << GUC_ELC_ENGINE_OFFSET);
+ (ring->id << GUC_ELC_ENGINE_OFFSET);
obj = ringbuf->obj;
-
lrc->ring_begin = i915_gem_obj_ggtt_offset(obj);
lrc->ring_end = lrc->ring_begin + obj->base.size - 1;
lrc->ring_next_free_location = lrc->ring_begin;
@@ -438,22 +432,16 @@ static void guc_init_ctx_desc(struct intel_guc *guc,
WARN_ON(desc.engines_used == 0);
/*
- * The CPU address is only needed at certain points, so kmap_atomic on
- * demand instead of storing it in the ctx descriptor.
+ * The CPU address is only needed at certain points, so kmap_atomic
+ * on demand instead of storing it in the ctx descriptor.
* XXX: May make debug easier to have it mapped
*/
desc.db_trigger_cpu = 0;
- desc.db_trigger_uk = client->doorbell_offset +
- i915_gem_obj_ggtt_offset(client->client_obj);
- desc.db_trigger_phy = client->doorbell_offset +
- sg_dma_address(client->client_obj->pages->sgl);
-
- desc.process_desc = client->proc_desc_offset +
- i915_gem_obj_ggtt_offset(client->client_obj);
-
- desc.wq_addr = client->wq_offset +
- i915_gem_obj_ggtt_offset(client->client_obj);
-
+ desc.db_trigger_phy = sg_dma_address(client->client_obj->pages->sgl)
+ + client->doorbell_offset;
+ desc.db_trigger_uk = client->client_gtt + client->doorbell_offset;
+ desc.process_desc = client->client_gtt + client->proc_desc_offset;
+ desc.wq_addr = client->client_gtt + client->wq_offset;
desc.wq_size = client->wq_size;
/*
@@ -766,6 +754,7 @@ static struct i915_guc_client *guc_client_alloc(struct drm_device *dev,
goto err;
client->client_obj = obj;
+ client->client_gtt = i915_gem_obj_ggtt_offset(obj);
client->wq_offset = GUC_DB_SIZE;
client->wq_size = GUC_WQ_SIZE;
spin_lock_init(&client->wq_lock);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 5ba5866..386e79a 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -28,21 +28,21 @@
#include "i915_guc_reg.h"
struct i915_guc_client {
- struct drm_i915_gem_object *client_obj;
- struct intel_context *owner;
struct intel_guc *guc;
+ struct intel_context *owner;
+ struct drm_i915_gem_object *client_obj;
+ uint64_t client_gtt; /* GTT offset of client_obj */
uint32_t priority;
uint32_t ctx_index;
- uint32_t proc_desc_offset;
- uint32_t doorbell_offset;
- uint32_t cookie;
+ uint32_t doorbell_offset; /* offset within client obj */
+ uint32_t proc_desc_offset; /* offset within client_obj */
+ uint32_t wq_offset; /* offset within client_obj */
+ uint32_t wq_size;
+ uint32_t doorbell_cookie;
uint16_t doorbell_id;
uint16_t padding; /* Maintain alignment */
- uint32_t wq_offset;
- uint32_t wq_size;
-
spinlock_t wq_lock; /* Protects all data below */
uint32_t wq_tail;
--
1.9.1
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