>-----Original Message----- >From: Intel-gfx [mailto:intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx] On Behalf Of Rodrigo Vivi >Sent: Thursday, November 19, 2015 6:10 AM >To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx >Cc: Vivi, Rodrigo >Subject: [PATCH 2/3] drm/i915: Remove PSR Perf Counter for SKL+ > >Whenever DMC firmware put the HW into DC State a bunch >of registers including this perf counter is reset to 0 and >never restored. > >So, even with PSR active and working we could still read >"Performance_Counter: 0" what will misslead people to believe >PSR is broken. > >So, it is better to remove this counter information while >we don't have a better way to track PSR residency. Agreed.. Reviewed-by: Durgadoss R <durgadoss.r@xxxxxxxxx> Thanks, Durga > >Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> >--- > drivers/gpu/drm/i915/i915_debugfs.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > >diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c >index 038d5c6..71e1666 100644 >--- a/drivers/gpu/drm/i915/i915_debugfs.c >+++ b/drivers/gpu/drm/i915/i915_debugfs.c >@@ -2580,8 +2580,11 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) > } > seq_puts(m, "\n"); > >- /* CHV PSR has no kind of performance counter */ >- if (HAS_DDI(dev)) { >+ /* >+ * VLV/CHV PSR has no kind of performance counter >+ * SKL+ Perf counter is reset to 0 everytime DC state is entered >+ */ >+ if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { > psrperf = I915_READ(EDP_PSR_PERF_CNT) & > EDP_PSR_PERF_CNT_MASK; > >-- >2.4.3 > >_______________________________________________ >Intel-gfx mailing list >Intel-gfx@xxxxxxxxxxxxxxxxxxxxx >http://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
