Hi,
Just applying this patch is enough to make gem_ringfill --r render work
on my SKL 2+2 DT GT2 system I have at Espoo. I do not need the second
patch which seems to be required for Arun's SKL.
Also working with just that patch on one SKL Y system here at Egham
office. It's some months older than Arun's SKL U.
Regards, Joonas
On ke, 2015-08-05 at 11:17 +0200, Daniel Vetter wrote:
> On Tue, Aug 04, 2015 at 10:01:43AM +0100, Siluvery, Arun wrote:
> > On 04/08/2015 09:58, Mika Kuoppala wrote:
> > > Ben Widawsky <benjamin.widawsky@xxxxxxxxx> writes:
> > >
> > > > On Mon, Aug 03, 2015 at 08:24:56PM +0100, Arun Siluvery wrote:
> > > > > Cc: Ben Widawsky <benjamin.widawsky@xxxxxxxxx>
> > > > > Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
> > > > > Signed-off-by: Arun Siluvery <arun.siluvery@xxxxxxxxxxxxxxx>
> > > > > ---
> > > > > drivers/gpu/drm/i915/i915_reg.h | 3 +++
> > > > > drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
> > > > > 2 files changed, 9 insertions(+)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > > index 77967ca..8991cd5 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > @@ -6849,6 +6849,9 @@ enum skl_disp_power_wells {
> > > > > #define GEN7_MISCCPCTL (0x9424)
> > > > > #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
> > > > >
> > > > > +#define GEN8_GARBCNTL 0xB004
> > > > > +#define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7)
> > > > > +
> > > > > /* IVYBRIDGE DPF */
> > > > > #define GEN7_L3CDERRST1 0xB008 /*
> > > > > L3CD Error Status 1 */
> > > > > #define HSW_L3CDERRST11 0xB208 /*
> > > > > L3CD Error Status register 1 slice 1 */
> > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > > > b/drivers/gpu/drm/i915/intel_pm.c
> > > > > index c23cab6..9152113 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > @@ -106,6 +106,12 @@ static void skl_init_clock_gating(struct
> > > > > drm_device *dev)
> > > > > /* WaDisableLSQCROPERFforOCL:skl */
> > > > > I915_WRITE(GEN8_L3SQCREG4,
> > > > > I915_READ(GEN8_L3SQCREG4) |
> > > > > GEN8_LQSC_RO_PERF_DIS);
> > > > > +
> > > > > + /* WaEnableGapsTsvCreditFix:skl */
> > > > > + if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >=
> > > > > SKL_REVID_C0)) {
> > > > > + I915_WRITE(GEN8_GARBCNTL,
> > > > > (I915_READ(GEN8_GARBCNTL) |
> > > > > +
> > > > > GEN9_GAPS_TSV_CREDIT_DISABLE));
> > > > > + }
> > > > > }
> > > > >
> > > > > static void bxt_init_clock_gating(struct drm_device *dev)
> > > >
> > > > FWIW, the docs make it sound like BIOS should be doing this.
> > > > Did you verify we
> > > > actually don't have the bit set with more recent BKC?
> > > >
> > >
> > > I have pretty recent BIOS and the bit was not set.
> >
> > I checked about this, it should be done in driver.
> >
> > regards
> > Arun
> >
> > >
> > > > Tested-by: Ben Widawsky <ben@xxxxxxxxxxxx>
> > > > Reviewed-by: Ben Widawsky <ben@xxxxxxxxxxxx>
> > > >
> > >
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90854
> > > Tested-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
>
> Queued for -next, thanks for the patch.
> -Daniel
>
> > >
> > > > --
> > > > Ben Widawsky, Intel Open Source Technology Center
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > >
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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