On Wed, Nov 04, 2015 at 11:20:00PM +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> If we ignore the BXT situation, we can observe that the only variables
> affecting gpio_mmio_base is IS_VALLEVIEW and HAS_GMCH_DISPLAY. The BXT
> situation we can fit into the same pattern if we change gmbus_pins_bxt[]
> to house the GMCH GPIO register offsets (like we do for all other
> platfotms). So let's do that.
>
> We could even simplify the VLV situation more by including the
> display_mmio_offset in the GPIO register defines, but let's leave it be
> for now.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_i2c.c | 15 +++++++--------
> 1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index bd58da0..9d35589 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -63,9 +63,9 @@ static const struct gmbus_pin gmbus_pins_skl[] = {
> };
>
> static const struct gmbus_pin gmbus_pins_bxt[] = {
> - [GMBUS_PIN_1_BXT] = { "dpb", PCH_GPIOB },
> - [GMBUS_PIN_2_BXT] = { "dpc", PCH_GPIOC },
> - [GMBUS_PIN_3_BXT] = { "misc", PCH_GPIOD },
> + [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
> + [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
> + [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
> };
>
> /* pin is expected to be valid */
> @@ -626,12 +626,11 @@ int intel_setup_gmbus(struct drm_device *dev)
>
> if (HAS_PCH_NOP(dev))
> return 0;
> - else if (HAS_PCH_SPLIT(dev))
> - dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
> - else if (IS_VALLEYVIEW(dev))
> +
> + if (IS_VALLEYVIEW(dev))
> dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
> - else
> - dev_priv->gpio_mmio_base = 0;
> + else if (!HAS_GMCH_DISPLAY(dev))
> + dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
>
> mutex_init(&dev_priv->gmbus_mutex);
> init_waitqueue_head(&dev_priv->gmbus_wait_queue);
> --
> 2.4.10
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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