Clear the pipe's dpll_hw_state when choosing the PLL for CRT on DDI
platforms. Otherwise stale values might cause the state checker to
complain.
Should fix errors like below:
[drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.wrpll
Cc: Gabriel Feceoru <gabriel.feceoru@xxxxxxxxx>
Cc: Daniel Vetter <daniel@xxxxxxxx>
Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@xxxxxxxxx>
---
*Completely untested*
drivers/gpu/drm/i915/intel_crt.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index b84aaa0..ad099f3 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -278,6 +278,9 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder,
/* FDI must always be 2.7 GHz */
if (HAS_DDI(dev)) {
+ memset(&pipe_config->dpll_hw_state, 0,
+ sizeof(pipe_config->dpll_hw_state));
+
pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;
pipe_config->port_clock = 135000 * 2;
}
--
2.4.3
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