This variable mostly doesn't reflect IPS enabled status
but its readiness.
This patch removes the only place where it was actually meaning ips
enabled, at crtc_load_lut workaround for Haswell only.
The actuall enabled will be properly implemented in a following patch.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_display.c | 19 +++++++++----------
drivers/gpu/drm/i915/intel_drv.h | 2 +-
2 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0811238..01da1c9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4534,7 +4534,7 @@ void hsw_enable_ips(struct intel_crtc *crtc)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- if (!crtc->config->ips_enabled)
+ if (!crtc->config->ips_ready)
return;
/* We can only enable IPS after we enable a plane and wait for a vblank */
@@ -4567,7 +4567,7 @@ void hsw_disable_ips(struct intel_crtc *crtc)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- if (!crtc->config->ips_enabled)
+ if (!crtc->config->ips_ready)
return;
assert_plane_enabled(dev_priv, crtc->plane);
@@ -4611,7 +4611,8 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
/* Workaround : Do not read or write the pipe palette/gamma data while
* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
*/
- if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
+ /* FIXME: This should be ips_enabled */
+ if (IS_HASWELL(dev) && intel_crtc->config->ips_ready &&
((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
GAMMA_MODE_MODE_SPLIT)) {
hsw_disable_ips(intel_crtc);
@@ -6558,7 +6559,7 @@ static void hsw_compute_ips_config(struct intel_crtc *crtc,
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- pipe_config->ips_enabled = i915.enable_ips &&
+ pipe_config->ips_ready = i915.enable_ips &&
hsw_crtc_supports_ips(crtc) &&
pipe_config_supports_ips(dev_priv, pipe_config);
}
@@ -9511,7 +9512,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
pixel_rate = ilk_pipe_pixel_rate(crtc_state);
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
- if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
+ if (IS_BROADWELL(state->dev) && crtc_state->ips_ready)
pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
max_pixel_rate = max(max_pixel_rate, pixel_rate);
@@ -9830,9 +9831,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
ironlake_get_pfit_config(crtc, pipe_config);
}
- if (IS_HASWELL(dev))
- pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
- (I915_READ(IPS_CTL) & IPS_ENABLE);
+ pipe_config->ips_ready = hsw_crtc_supports_ips(crtc);
if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
pipe_config->pixel_multiplier =
@@ -12001,7 +12000,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
pipe_config->pch_pfit.pos,
pipe_config->pch_pfit.size,
pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
- DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
+ DRM_DEBUG_KMS("ips ready: %i\n", pipe_config->ips_ready);
DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
if (IS_BROXTON(dev)) {
@@ -12553,7 +12552,7 @@ intel_pipe_config_compare(struct drm_device *dev,
/* BDW+ don't expose a synchronous way to read the state */
if (IS_HASWELL(dev))
- PIPE_CONF_CHECK_I(ips_enabled);
+ PIPE_CONF_CHECK_I(ips_ready);
PIPE_CONF_CHECK_I(double_wide);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 92518b4..2aae219 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -476,7 +476,7 @@ struct intel_crtc_state {
int fdi_lanes;
struct intel_link_m_n fdi_m_n;
- bool ips_enabled;
+ bool ips_ready;
bool double_wide;
--
2.4.3
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