tree: git://anongit.freedesktop.org/drm-intel drm-intel-nightly
head: fba7fdd3589b453770f28caa39064b6c0141e81a
commit: b8a8f412df08b100bbb6845c50f73656d677d08a [4/8] Merge remote-tracking branch 'drm-upstream/drm-next' into drm-intel-nightly
config: x86_64-randconfig-x007-10252017 (attached as .config)
reproduce:
git checkout b8a8f412df08b100bbb6845c50f73656d677d08a
# save the attached .config to linux build tree
make ARCH=x86_64
All error/warnings (new ones prefixed by >>):
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c: In function 'dce_v10_0_resume':
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3143:13: error: invalid storage class for function 'dce_v10_0_is_idle'
static bool dce_v10_0_is_idle(void *handle)
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3143:1: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement]
static bool dce_v10_0_is_idle(void *handle)
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3148:12: error: invalid storage class for function 'dce_v10_0_wait_for_idle'
static int dce_v10_0_wait_for_idle(void *handle)
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3153:13: error: invalid storage class for function 'dce_v10_0_print_status'
static void dce_v10_0_print_status(void *handle)
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3161:12: error: invalid storage class for function 'dce_v10_0_soft_reset'
static int dce_v10_0_soft_reset(void *handle)
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3191:13: error: invalid storage class for function 'dce_v10_0_set_crtc_vblank_interrupt_state'
static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3220:13: error: invalid storage class for function 'dce_v10_0_set_crtc_vline_interrupt_state'
static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3249:12: error: invalid storage class for function 'dce_v10_0_set_hpd_irq_state'
static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3279:12: error: invalid storage class for function 'dce_v10_0_set_crtc_irq_state'
static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3327:12: error: invalid storage class for function 'dce_v10_0_set_pageflip_irq_state'
static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3350:12: error: invalid storage class for function 'dce_v10_0_pageflip_irq'
static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3403:13: error: invalid storage class for function 'dce_v10_0_hpd_int_ack'
static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3418:13: error: invalid storage class for function 'dce_v10_0_crtc_vblank_int_ack'
static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3433:13: error: invalid storage class for function 'dce_v10_0_crtc_vline_int_ack'
static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3448:12: error: invalid storage class for function 'dce_v10_0_crtc_irq'
static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3486:12: error: invalid storage class for function 'dce_v10_0_hpd_irq'
static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3511:12: error: invalid storage class for function 'dce_v10_0_set_clockgating_state'
static int dce_v10_0_set_clockgating_state(void *handle,
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3517:12: error: invalid storage class for function 'dce_v10_0_set_powergating_state'
static int dce_v10_0_set_powergating_state(void *handle,
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3541:1: error: invalid storage class for function 'dce_v10_0_encoder_mode_set'
dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
^
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c:3561:13: error: invalid storage class for function 'dce_v10_0_encoder_prepare'
static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
^
vim +/dce_v10_0_is_idle +3143 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
aaa36a97 Alex Deucher 2015-04-20 3137 dce_v10_0_hpd_init(adev);
aaa36a97 Alex Deucher 2015-04-20 3138
f6c7aba4 Michel Dänzer 2015-10-08 3139 dce_v10_0_pageflip_interrupt_init(adev);
f6c7aba4 Michel Dänzer 2015-10-08 3140
f9fff064 Alex Deucher 2015-10-15 3141 return ret;
aaa36a97 Alex Deucher 2015-04-20 3142
5fc3aeeb yanyang1 2015-05-22 @3143 static bool dce_v10_0_is_idle(void *handle)
aaa36a97 Alex Deucher 2015-04-20 3144 {
aaa36a97 Alex Deucher 2015-04-20 3145 return true;
aaa36a97 Alex Deucher 2015-04-20 3146 }
aaa36a97 Alex Deucher 2015-04-20 3147
5fc3aeeb yanyang1 2015-05-22 @3148 static int dce_v10_0_wait_for_idle(void *handle)
aaa36a97 Alex Deucher 2015-04-20 3149 {
aaa36a97 Alex Deucher 2015-04-20 3150 return 0;
aaa36a97 Alex Deucher 2015-04-20 3151 }
aaa36a97 Alex Deucher 2015-04-20 3152
5fc3aeeb yanyang1 2015-05-22 @3153 static void dce_v10_0_print_status(void *handle)
aaa36a97 Alex Deucher 2015-04-20 3154 {
5fc3aeeb yanyang1 2015-05-22 3155 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5fc3aeeb yanyang1 2015-05-22 3156
aaa36a97 Alex Deucher 2015-04-20 3157 dev_info(adev->dev, "DCE 10.x registers\n");
aaa36a97 Alex Deucher 2015-04-20 3158 /* XXX todo */
aaa36a97 Alex Deucher 2015-04-20 3159 }
aaa36a97 Alex Deucher 2015-04-20 3160
5fc3aeeb yanyang1 2015-05-22 @3161 static int dce_v10_0_soft_reset(void *handle)
aaa36a97 Alex Deucher 2015-04-20 3162 {
aaa36a97 Alex Deucher 2015-04-20 3163 u32 srbm_soft_reset = 0, tmp;
5fc3aeeb yanyang1 2015-05-22 3164 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97 Alex Deucher 2015-04-20 3165
aaa36a97 Alex Deucher 2015-04-20 3166 if (dce_v10_0_is_display_hung(adev))
aaa36a97 Alex Deucher 2015-04-20 3167 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
aaa36a97 Alex Deucher 2015-04-20 3168
aaa36a97 Alex Deucher 2015-04-20 3169 if (srbm_soft_reset) {
5fc3aeeb yanyang1 2015-05-22 3170 dce_v10_0_print_status((void *)adev);
aaa36a97 Alex Deucher 2015-04-20 3171
aaa36a97 Alex Deucher 2015-04-20 3172 tmp = RREG32(mmSRBM_SOFT_RESET);
aaa36a97 Alex Deucher 2015-04-20 3173 tmp |= srbm_soft_reset;
aaa36a97 Alex Deucher 2015-04-20 3174 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
aaa36a97 Alex Deucher 2015-04-20 3175 WREG32(mmSRBM_SOFT_RESET, tmp);
aaa36a97 Alex Deucher 2015-04-20 3176 tmp = RREG32(mmSRBM_SOFT_RESET);
aaa36a97 Alex Deucher 2015-04-20 3177
aaa36a97 Alex Deucher 2015-04-20 3178 udelay(50);
aaa36a97 Alex Deucher 2015-04-20 3179
aaa36a97 Alex Deucher 2015-04-20 3180 tmp &= ~srbm_soft_reset;
aaa36a97 Alex Deucher 2015-04-20 3181 WREG32(mmSRBM_SOFT_RESET, tmp);
aaa36a97 Alex Deucher 2015-04-20 3182 tmp = RREG32(mmSRBM_SOFT_RESET);
aaa36a97 Alex Deucher 2015-04-20 3183
aaa36a97 Alex Deucher 2015-04-20 3184 /* Wait a little for things to settle down */
aaa36a97 Alex Deucher 2015-04-20 3185 udelay(50);
5fc3aeeb yanyang1 2015-05-22 3186 dce_v10_0_print_status((void *)adev);
aaa36a97 Alex Deucher 2015-04-20 3187 }
aaa36a97 Alex Deucher 2015-04-20 3188 return 0;
aaa36a97 Alex Deucher 2015-04-20 3189 }
aaa36a97 Alex Deucher 2015-04-20 3190
aaa36a97 Alex Deucher 2015-04-20 @3191 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
aaa36a97 Alex Deucher 2015-04-20 3192 int crtc,
aaa36a97 Alex Deucher 2015-04-20 3193 enum amdgpu_interrupt_state state)
aaa36a97 Alex Deucher 2015-04-20 3194 {
aaa36a97 Alex Deucher 2015-04-20 3195 u32 lb_interrupt_mask;
aaa36a97 Alex Deucher 2015-04-20 3196
aaa36a97 Alex Deucher 2015-04-20 3197 if (crtc >= adev->mode_info.num_crtc) {
aaa36a97 Alex Deucher 2015-04-20 3198 DRM_DEBUG("invalid crtc %d\n", crtc);
aaa36a97 Alex Deucher 2015-04-20 3199 return;
aaa36a97 Alex Deucher 2015-04-20 3200 }
aaa36a97 Alex Deucher 2015-04-20 3201
aaa36a97 Alex Deucher 2015-04-20 3202 switch (state) {
aaa36a97 Alex Deucher 2015-04-20 3203 case AMDGPU_IRQ_STATE_DISABLE:
aaa36a97 Alex Deucher 2015-04-20 3204 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
aaa36a97 Alex Deucher 2015-04-20 3205 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
aaa36a97 Alex Deucher 2015-04-20 3206 VBLANK_INTERRUPT_MASK, 0);
aaa36a97 Alex Deucher 2015-04-20 3207 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
aaa36a97 Alex Deucher 2015-04-20 3208 break;
aaa36a97 Alex Deucher 2015-04-20 3209 case AMDGPU_IRQ_STATE_ENABLE:
aaa36a97 Alex Deucher 2015-04-20 3210 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
aaa36a97 Alex Deucher 2015-04-20 3211 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
aaa36a97 Alex Deucher 2015-04-20 3212 VBLANK_INTERRUPT_MASK, 1);
aaa36a97 Alex Deucher 2015-04-20 3213 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
aaa36a97 Alex Deucher 2015-04-20 3214 break;
aaa36a97 Alex Deucher 2015-04-20 3215 default:
aaa36a97 Alex Deucher 2015-04-20 3216 break;
aaa36a97 Alex Deucher 2015-04-20 3217 }
aaa36a97 Alex Deucher 2015-04-20 3218 }
aaa36a97 Alex Deucher 2015-04-20 3219
aaa36a97 Alex Deucher 2015-04-20 @3220 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
aaa36a97 Alex Deucher 2015-04-20 3221 int crtc,
aaa36a97 Alex Deucher 2015-04-20 3222 enum amdgpu_interrupt_state state)
aaa36a97 Alex Deucher 2015-04-20 3223 {
aaa36a97 Alex Deucher 2015-04-20 3224 u32 lb_interrupt_mask;
aaa36a97 Alex Deucher 2015-04-20 3225
aaa36a97 Alex Deucher 2015-04-20 3226 if (crtc >= adev->mode_info.num_crtc) {
aaa36a97 Alex Deucher 2015-04-20 3227 DRM_DEBUG("invalid crtc %d\n", crtc);
aaa36a97 Alex Deucher 2015-04-20 3228 return;
aaa36a97 Alex Deucher 2015-04-20 3229 }
aaa36a97 Alex Deucher 2015-04-20 3230
aaa36a97 Alex Deucher 2015-04-20 3231 switch (state) {
aaa36a97 Alex Deucher 2015-04-20 3232 case AMDGPU_IRQ_STATE_DISABLE:
aaa36a97 Alex Deucher 2015-04-20 3233 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
aaa36a97 Alex Deucher 2015-04-20 3234 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
aaa36a97 Alex Deucher 2015-04-20 3235 VLINE_INTERRUPT_MASK, 0);
aaa36a97 Alex Deucher 2015-04-20 3236 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
aaa36a97 Alex Deucher 2015-04-20 3237 break;
aaa36a97 Alex Deucher 2015-04-20 3238 case AMDGPU_IRQ_STATE_ENABLE:
aaa36a97 Alex Deucher 2015-04-20 3239 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
aaa36a97 Alex Deucher 2015-04-20 3240 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
aaa36a97 Alex Deucher 2015-04-20 3241 VLINE_INTERRUPT_MASK, 1);
aaa36a97 Alex Deucher 2015-04-20 3242 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
aaa36a97 Alex Deucher 2015-04-20 3243 break;
aaa36a97 Alex Deucher 2015-04-20 3244 default:
aaa36a97 Alex Deucher 2015-04-20 3245 break;
aaa36a97 Alex Deucher 2015-04-20 3246 }
aaa36a97 Alex Deucher 2015-04-20 3247 }
aaa36a97 Alex Deucher 2015-04-20 3248
aaa36a97 Alex Deucher 2015-04-20 @3249 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
aaa36a97 Alex Deucher 2015-04-20 3250 struct amdgpu_irq_src *source,
aaa36a97 Alex Deucher 2015-04-20 3251 unsigned hpd,
aaa36a97 Alex Deucher 2015-04-20 3252 enum amdgpu_interrupt_state state)
aaa36a97 Alex Deucher 2015-04-20 3253 {
aaa36a97 Alex Deucher 2015-04-20 3254 u32 tmp;
aaa36a97 Alex Deucher 2015-04-20 3255
aaa36a97 Alex Deucher 2015-04-20 3256 if (hpd >= adev->mode_info.num_hpd) {
aaa36a97 Alex Deucher 2015-04-20 3257 DRM_DEBUG("invalid hdp %d\n", hpd);
aaa36a97 Alex Deucher 2015-04-20 3258 return 0;
aaa36a97 Alex Deucher 2015-04-20 3259 }
aaa36a97 Alex Deucher 2015-04-20 3260
aaa36a97 Alex Deucher 2015-04-20 3261 switch (state) {
aaa36a97 Alex Deucher 2015-04-20 3262 case AMDGPU_IRQ_STATE_DISABLE:
aaa36a97 Alex Deucher 2015-04-20 3263 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
aaa36a97 Alex Deucher 2015-04-20 3264 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
aaa36a97 Alex Deucher 2015-04-20 3265 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
aaa36a97 Alex Deucher 2015-04-20 3266 break;
aaa36a97 Alex Deucher 2015-04-20 3267 case AMDGPU_IRQ_STATE_ENABLE:
aaa36a97 Alex Deucher 2015-04-20 3268 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
aaa36a97 Alex Deucher 2015-04-20 3269 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
aaa36a97 Alex Deucher 2015-04-20 3270 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
aaa36a97 Alex Deucher 2015-04-20 3271 break;
aaa36a97 Alex Deucher 2015-04-20 3272 default:
aaa36a97 Alex Deucher 2015-04-20 3273 break;
aaa36a97 Alex Deucher 2015-04-20 3274 }
aaa36a97 Alex Deucher 2015-04-20 3275
aaa36a97 Alex Deucher 2015-04-20 3276 return 0;
aaa36a97 Alex Deucher 2015-04-20 3277 }
aaa36a97 Alex Deucher 2015-04-20 3278
aaa36a97 Alex Deucher 2015-04-20 @3279 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
aaa36a97 Alex Deucher 2015-04-20 3280 struct amdgpu_irq_src *source,
aaa36a97 Alex Deucher 2015-04-20 3281 unsigned type,
aaa36a97 Alex Deucher 2015-04-20 3282 enum amdgpu_interrupt_state state)
aaa36a97 Alex Deucher 2015-04-20 3283 {
aaa36a97 Alex Deucher 2015-04-20 3284 switch (type) {
aaa36a97 Alex Deucher 2015-04-20 3285 case AMDGPU_CRTC_IRQ_VBLANK1:
aaa36a97 Alex Deucher 2015-04-20 3286 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
aaa36a97 Alex Deucher 2015-04-20 3287 break;
aaa36a97 Alex Deucher 2015-04-20 3288 case AMDGPU_CRTC_IRQ_VBLANK2:
aaa36a97 Alex Deucher 2015-04-20 3289 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
aaa36a97 Alex Deucher 2015-04-20 3290 break;
aaa36a97 Alex Deucher 2015-04-20 3291 case AMDGPU_CRTC_IRQ_VBLANK3:
aaa36a97 Alex Deucher 2015-04-20 3292 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
aaa36a97 Alex Deucher 2015-04-20 3293 break;
aaa36a97 Alex Deucher 2015-04-20 3294 case AMDGPU_CRTC_IRQ_VBLANK4:
aaa36a97 Alex Deucher 2015-04-20 3295 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
aaa36a97 Alex Deucher 2015-04-20 3296 break;
aaa36a97 Alex Deucher 2015-04-20 3297 case AMDGPU_CRTC_IRQ_VBLANK5:
aaa36a97 Alex Deucher 2015-04-20 3298 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
aaa36a97 Alex Deucher 2015-04-20 3299 break;
aaa36a97 Alex Deucher 2015-04-20 3300 case AMDGPU_CRTC_IRQ_VBLANK6:
aaa36a97 Alex Deucher 2015-04-20 3301 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
aaa36a97 Alex Deucher 2015-04-20 3302 break;
aaa36a97 Alex Deucher 2015-04-20 3303 case AMDGPU_CRTC_IRQ_VLINE1:
aaa36a97 Alex Deucher 2015-04-20 3304 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
aaa36a97 Alex Deucher 2015-04-20 3305 break;
aaa36a97 Alex Deucher 2015-04-20 3306 case AMDGPU_CRTC_IRQ_VLINE2:
aaa36a97 Alex Deucher 2015-04-20 3307 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
aaa36a97 Alex Deucher 2015-04-20 3308 break;
aaa36a97 Alex Deucher 2015-04-20 3309 case AMDGPU_CRTC_IRQ_VLINE3:
aaa36a97 Alex Deucher 2015-04-20 3310 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
aaa36a97 Alex Deucher 2015-04-20 3311 break;
aaa36a97 Alex Deucher 2015-04-20 3312 case AMDGPU_CRTC_IRQ_VLINE4:
aaa36a97 Alex Deucher 2015-04-20 3313 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
aaa36a97 Alex Deucher 2015-04-20 3314 break;
aaa36a97 Alex Deucher 2015-04-20 3315 case AMDGPU_CRTC_IRQ_VLINE5:
aaa36a97 Alex Deucher 2015-04-20 3316 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
aaa36a97 Alex Deucher 2015-04-20 3317 break;
aaa36a97 Alex Deucher 2015-04-20 3318 case AMDGPU_CRTC_IRQ_VLINE6:
aaa36a97 Alex Deucher 2015-04-20 3319 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
aaa36a97 Alex Deucher 2015-04-20 3320 break;
aaa36a97 Alex Deucher 2015-04-20 3321 default:
aaa36a97 Alex Deucher 2015-04-20 3322 break;
aaa36a97 Alex Deucher 2015-04-20 3323 }
aaa36a97 Alex Deucher 2015-04-20 3324 return 0;
aaa36a97 Alex Deucher 2015-04-20 3325 }
aaa36a97 Alex Deucher 2015-04-20 3326
aaa36a97 Alex Deucher 2015-04-20 @3327 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
aaa36a97 Alex Deucher 2015-04-20 3328 struct amdgpu_irq_src *src,
aaa36a97 Alex Deucher 2015-04-20 3329 unsigned type,
aaa36a97 Alex Deucher 2015-04-20 3330 enum amdgpu_interrupt_state state)
:::::: The code at line 3143 was first introduced by commit
:::::: 5fc3aeeb9e553a20ce62544f7176c6c4aca52d71 drm/amdgpu: rename amdgpu_ip_funcs to amd_ip_funcs (v2)
:::::: TO: yanyang1 <young.yang@xxxxxxx>
:::::: CC: Alex Deucher <alexander.deucher@xxxxxxx>
---
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